參數(shù)資料
型號： ADA4084-2ARZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 16/29頁
文件大?。?/td> 0K
描述： IC OPAMP GP RRIO 10MHZ DL 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 通用
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 4.6 V/µs
增益帶寬積： 15.9MHz
-3db帶寬： 13.9MHz
電流 - 輸入偏壓： 140nA
電壓 - 輸入偏移： 100µV
電流 - 電源： 625µA
電流 - 輸出 / 通道： 30mA
電壓 - 電源，單路/雙路(±)： 4 V ~ 36 V，±2 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
ADA4084-2
Data Sheet
Rev. C | Page 22 of 28
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADA4084-2 is a precision single-supply, rail-to-rail operational
amplifier. Intended for portable instrumentation, the ADA4084-2
combines the attributes of precision, wide bandwidth, and low noise
to make it an ideal choice in single-supply applications that require
both ac and precision dc performance. Other low supply voltage
applications for which the ADA4084-2 is well suited are active filters,
audio microphone preamplifiers, power supply control, and tele-
communications. To combine all of these attributes with rail-to-rail
input/output operation, novel circuit design techniques are used.
D2
D101
D100
D5
D4
D1
Q1
Q4
Q3
Q2
08237-
073
R4
R1
R2
R3
Figure 78. ADA4084-2 Equivalent Input Circuit
For example, Figure 78 illustrates a simplified equivalent circuit for
the input stage of the ADA4084-2. It comprises a PNP differential
pair, Q1 and Q2, and an NPN differential pair, Q3 and Q4,
operating concurrently. Diode D100 and Diode D101 serve to
clamp the applied differential input voltage to the ADA4084-2,
thereby protecting the input transistors against Zener breakdown
of the emitter-base junctions. Input stage voltage gains are kept
low for input rail-to-rail operation. The two pairs of differential
output voltages are connected to the second stage of the ADA4084-2,
which is a modified compound folded cascade gain stage. It is also
in the second gain stage, where the two pairs of differential output
voltages are combined into a single-ended output signal voltage
used to drive the output stage.
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-2 are the arithmetic sum of the base
currents in Q1 and Q4 and in Q2 and Q3. As a result of this design
approach, the input bias currents in the ADA4084-2 not only
exhibit different amplitudes; they also exhibit different polarities.
This effect is best illustrated by Figure 9, Figure 10, Figure 34,
Figure 35, Figure 59, and Figure 60. It is therefore important
that the effective source impedances connected to the ADA4084-2
inputs be balanced for optimum dc and ac performance.
To achieve rail-to-rail output, the ADA4084-2 output stage
design employs a unique topology for both sourcing and sinking
current. This circuit topology is illustrated in Figure 79. The
output stage is voltage-driven from the second gain stage. The
signal path through the output stage is inverting; that is, for
positive input signals, Q13 provides the base current drive to Q19
so that it conducts (sinks) current. For negative input signals, the
signal path via Q18 → mirror → Q24 provides the base current
drive for Q23 to conduct (source) current. Both transistors
provide output current until they are forced into saturation.
Q24
Q21
D20
Q13
Q18
Q19
Q23
VEE
VOUT
VCC
VBIAS
MIRROR
08237-
074
R5
R6
R7 C2
C1
Figure 79. ADA4084-2 Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-2 maximum output voltage swing. Output
short-circuit current limiting is determined by the maximum
signal current into the base of Q13 from the second gain stage.
The output stage also exhibits voltage gain. This is accomplished
by the use of common-emitter amplifiers, and, as a result, the
voltage gain of the output stage (thus, the open-loop gain of the
device) exhibits a dependence on the total load resistance at the
output of the ADA4084-2.
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