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參數資料
| 型號： | ADA4817-1ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF 410MHZ LN 8LFCSP |
| 標準包裝： | 1 |
| 系列： | FastFET™ |
| 放大器類型： | 電壓反饋 |
| 電路數： | 1 |
| 轉換速率： | 870 V/µs |
| 增益帶寬積： | 410MHz |
| -3db帶寬： | 1.05GHz |
| 電流 - 輸入偏壓： | 2pA |
| 電壓 - 輸入偏移： | 400µV |
| 電流 - 電源： | 19mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 10 V，±2.5 V ~ 5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 8-LFCSP-VD（3x3） |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 768 (CN2011-ZH PDF) |
| 其它名稱： | ADA4817-1ACPZ-R7DKR |
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Data Sheet
ADA4817-1/ADA4817-2
Rev. B | Page 15 of 28
The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG
(though with the ADA4817-1/ADA4817-2 input currents in the
picoamp range, this is likely not a concern). To include common-
mode effects and power supply rejection effects, total VOS can be
modeled by
CMR
V
PSR
V
CM
S
nom
OS
Δ
+
=
(11)
where:
nom
OS
V
is the offset voltage specified at nominal conditions.
ΔVS is the change in power supply from nominal conditions.
PSR is the power supply rejection.
ΔVCM is the change in common-mode voltage from nominal
conditions.
CMR is the common-mode rejection.
WIDEBAND OPERATION
The ADA4817-1/ADA4817-2 provides excellent performance as
a high speed buffer. Figure 41 shows the circuit used for wideband
characterization for high gains. The impedance at the summing
junction (RF || RG) forms a pole in the loop response of the amp-
lifier with the amplifier’s input capacitance of 1.3 pF. This pole
can cause peaking and ringing if its frequency is too low. Feed-
back resistances of 100 to 400 are recommended because
they minimize the peaking and they do not degrade the
performance of the output stage. Peaking in the frequency
response can also be compensated for with a small feedback
capacitor (CF) in parallel with the feedback resistor, or a series
resistor in the noninverting input, as shown in Figure 45.
The distortion performance depends on a number of variables:
The closed-loop gain of the application
Whether it is inverting or noninverting
Amplifier loading
Signal frequency and amplitude
Board layout
The best performance is usually obtained in the G + 1
configuration with no feedback resistance, big output
load resistors, and small board parasitic capacitances.
DRIVING CAPACITIVE LOADS
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest. The difficulty
arises because the load capacitance, CL, forms a pole with the
output resistance, RO, of the amplifier. The pole can be described
by the following equation:
L
O
P
C
R
f
2π
1
=
(12)
If this pole occurs too close to the unity-gain crossover point,
the phase margin degrades. This is due to the additional phase
loss associated with the pole.
Note that such capacitance introduces significant peaking in the
frequency response. Larger capacitance values can be driven but
must use a snubbing resistor (RSNUB) at the output of the amplifier,
a zero that cancels the pole introduced by the load capacitance.
Typical values for RSNUB can range from 10 to 50 . The value is
typically based on the circuit requirements. Figure 45 also shows
another way to reduce the effect of the pole created by the capacitive
load (CL) by placing a capacitor (CF) in the feedback loop parallel
to the feedback resistor Typical capacitor values can range from
0.5 pF to 2 pF. Figure 46 shows the effect of adding a feedback
capacitor to the frequency response.
VIN
VOUT
0.1F
10F
+VS
–VS
49.9
RL
0.1F
CL
+
10F
+
RF
RSNUB
CF
RG
07756-
143
Figure 45. RSNUB or CF Used to Reduce Peaking
THERMAL CONSIDERATIONS
With 10 V power supplies and 19 mA quiescent current, the
ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This
implies that in the LFCSP, whose thermal resistance is 94°C/W for
the ADA4817-1 and 64°C/W for the ADA4817-2, the junction
temperature is typically almost 25° higher than the ambient tem-
perature. The ADA4817-1/ADA4817-2 are designed to maintain a
constant bandwidth over temperature; therefore, an initial ramp up
of the current consumption during warm-up is expected. The VOS
temperature drift is below 8 V/°C; therefore, it can change up to
0.3 mV due to warm-up effects for an ADA4817-1/ADA4817-2
in a LFCSP on 10 V. The input bias current increases by a factor
of 1.7 for every 10°C rise in temperature.
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Absolute Maximum
Ratings section. Take care not to exceed the rated power
dissipation of the package.
POWER-DOWN OPERATION
The ADA4817-1/ADA4817-2 are equipped with separate power-
down pins (PD) for each amplifier. This allows the user the ability
to reduce the quiescent supply current when an amplifier is
inactive from 19 mA to below 2 mA. The power-down threshold
levels are derived from the voltage applied to the +VS pin. In ±5 V
supply application, the enable voltage is greater than +4 V, and in a
+3 V, 2 V supply application, the enable voltage is greater than
+2 V. However, the amplifier is powered down whenever the
voltage applied to PD is 3 V below +VS. If the PD pin is not used,
connect it to the positive supply to ensure proper start-up.
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