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參數(shù)資料
| 型號： | ADA4817-1ARD-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADA4817 SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 電壓反饋 |
| 板類型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 8-SOIC 封裝 |
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Data Sheet
ADA4817-1/ADA4817-2
Rev. B | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
10.6 V
Power Dissipation
Common-Mode Input Voltage
VS 0.5 V to +VS + 0.5 V
Differential Input Voltage
±VS
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +105°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board for the
surface-mount packages.
Table 4.
Package Type
θJA
θJC
Unit
LFCSP_VD (ADA4817-1)
94
29
°C/W
SOIC_N_EP (ADA4817-1)
79
29
°C/W
LFCSP_WQ (ADA4817-2)
64
14
°C/W
MAXIMUM SAFE POWER DISSIPATION
The maximum safe power dissipation for the ADA4817-1/
ADA4817-2 are limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C (which is
the glass transition temperature), the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4817-x. Exceeding
a junction temperature of 175°C for an extended period can result
in changes in silicon devices, potentially causing degradation or
loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4817-1/ADA4817-2 drive at the output.
The quiescent power is the voltage between the supply pins (VS)
multiplied by the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power) (1)
(
)
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
–
2
×
+
×
=
(2)
Consider RMS output voltages. If RL is referenced to VS, as
in single-supply operation, the total drive power is VS × IOUT. If
the rms signal levels are indeterminate, consider the worst-case
scenario, when VOUT = VS/4 for RL to midsupply.
(
) (
)
L
S
D
R
V
I
V
P
2
4
/
+
×
=
(3)
In single-supply operation with RL referenced to VS, the worst-
case situation is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
More metal directly in contact with the package leads and
exposed paddle from metal traces, throughholes, ground,
and power planes also reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
LFCSP_VD (single 94°C/W), SOIC_N_EP (single 79°C/W)
and LFCSP_WQ (dual 64°C/W) package on a JEDEC standard
4-layer board. θJA values are approximations.
3.5
0
–40
AMBIENT TEMPERATURE (°C)
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
3.0
2.5
2.0
1.5
1.0
0.5
–30 –20 –10
0
10
20
30
40
50
60
70
80
90 100
ADA4817-1, LFCSP
ADA4817-2, LFCSP
07756-
008
ADA4817-1, SOIC
Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
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