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| 型號： | ADA4856-3YCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP 3CH RRO VFB G=+2 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 應(yīng)用： | 電壓反饋 |
| 輸出類型： | 滿擺幅 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 370MHz |
| 轉(zhuǎn)換速率： | 800 V/µs |
| 電流 - 電源： | 7.8mA |
| 電流 - 輸出 / 通道： | 52mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V，±1.5 V ~ 2.75 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ EP（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADA4856-3
Rev. B | Page 13 of 20
APPLICATIONS INFORMATION
USING THE ADA4856-3 IN GAINS EQUAL TO +1, 1
The ADA4856-3 was designed to offer outstanding video
performance, simplify applications, and minimize board area.
The ADA4856-3 is a triple amplifier with on-chip feedback
and gain set resistors. The gain is fixed internally at G = +2. The
inclusion of the on-chip resistors not only simplifies the design of
the application but also eliminates six surface-mount resistors,
saving valuable board space and lowering assembly costs.
Whereas the ADA4856-3 has a fixed gain of G = +2, it can be
used in other gain configurations, such as G = 1 and G = +1.
Unity-Gain Operation
Option 1
There are two options for obtaining unity gain (G = +1). The
first is shown in Figure 34. In this configuration, the –IN input
pin is tied to the output (feedback is now provided with the two
internal 402 Ω resistors in parallel), and the input is applied to
the noninverting input. The noise gain for this configuration is 1.
07
68
6-
0
32
0.1F
VIN
RT
VOUT
+VS
–VS
GAIN OF +1
10F
Figure 34. Unity Gain of Option 1
Option 2
Another option exists for running the ADA4856-3 as a unity-
gain amplifier. In this configuration, the noise gain is +2, see
Figure 35. The frequency response and transient response for
this configuration closely match the gain of +2 plots because the
noise gains are equal. This method does have twice the noise gain
of Option 1; however, in applications that do not require low noise,
Option 2 offers less peaking and ringing. By tying the inputs
together, the net gain of the amplifier becomes 1. Equation 1 shows
the transfer characteristic for the schematic shown in Figure 35.
G
F
IN
G
F
IN
OUT
R
V
R
V
(1)
which simplifies to VOUT = VIN.
0.1F
VIN
RT
RG
RF
VOUT
+VS
–VS
GAIN OF +1
0
768
6-
0
30
10F
Figure 35. Unity Gain of Option 2
Inverting Unity-Gain Operation
In this configuration, the noninverting input is tied to ground
and the input signal is applied to the inverting input. The noise
gain for this configuration is +2, see Figure 36.
0.1F
VIN
RT
VOUT
+VS
–VS
GAIN OF –1
07
68
6-
03
1
10F
Figure 36. Inverting Configuration (G = 1)
Figure 37 shows the small signal frequency response for both
gain of +1 (Option 1 and Option 2) and gain of 1 configurations.
It is clear that G = +1, Option 2 has better flatness and no peaking
compared to Option 1.
6
3
0
–3
–6
–9
–12
1
10
100
1000
M
A
GN
ITU
D
E
(
d
B
)
FREQUENCY (MHz)
07
68
6-
0
44
VS = 5V
RL = 100
VOUT = 100mV p-p
OPTION 1
G = +1
OPTION 2
G = +1
G = –1
Figure 37. G = +1 and G = 1
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