參數(shù)資料
型號: ADA4857-1YRZ
廠商: Analog Devices Inc
文件頁數(shù): 8/20頁
文件大小: 0K
描述: IC OPAMP VF ULDIST LP LN 8SOIC
標(biāo)準(zhǔn)包裝: 98
放大器類型: 電壓反饋
電路數(shù): 1
轉(zhuǎn)換速率: 2800 V/µs
-3db帶寬: 850MHz
電流 - 輸入偏壓: 2µA
電壓 - 輸入偏移: 2000µV
電流 - 電源: 5mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 10.5 V,±2.25 V ~ 5.25 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁面: 768 (CN2011-ZH PDF)
ADA4857-1/ADA4857-2
Data Sheet
Rev. C | Page 16 of 20
APPLICATIONS INFORMATION
POWER-DOWN OPERATION
The PD pin is used to power down the chip, which reduces the
quiescent current and the overall power consumption. It is low
enabled, which means that the chip is on with full power when
the PD pin input voltage is low (see Table 8). Note that PD does not
put the output in a high-Z state, which means that the ADA4857
should not be used as a multiplexer.
Table 8. PD Operation Table Guide
Supply Voltage
Condition
±5 V
±2.5 V
+5 V
Enabled
≤+0.8 V
≤1.7 V
≤+0.8 V
Powered down
≥+3 V
≥+0.5 V
≥+3 V
CAPACITIVE LOAD CONSIDERATIONS
When driving a capacitive load using the SOIC package, RSNUB is
used to reduce the peaking (see Figure 47). An optimum resistor
value of 40 is found to maintain the peaking within 1 dB for
any capacitive load up to 40 pF.
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 9 provides a useful reference for determining various gains
and associated performance. RF and RG are kept low to minimize
their contribution to the overall noise performance of the amplifier.
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 k, RT = 49.9
Gain
RS () (CSP/SOIC)
RF ()
RG ()
3 dB SS BW (MHz)
(CSP/SOIC)
Slew Rate (V/s),
VOUT = 2 V Step
ADA4857 Voltage
Noise (nV/√Hz), RTO
Total System
Noise (nV/√Hz), RTO
+1
0/100
0
N/A
850/750
2350
4.4
4.49
+2
0/0
499
360/320
1680
8.8
9.89
+5
0/0
499
124
90/89
516
22.11
23.49
+10
0/0
499
56.2
43/40
213
43.47
45.31
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