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參數(shù)資料
| 型號： | ADA4891-4ARZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP GP R-R CMOS 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 210 V/µs |
| -3db帶寬： | 240MHz |
| 電流 - 輸入偏壓： | 2pA |
| 電壓 - 輸入偏移： | 2500µV |
| 電流 - 電源： | 4.4mA |
| 電流 - 輸出 / 通道： | 125mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 5.5 V，±1.35 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Rev. E | Page 17 of 24
08054-
025
–0.3
–0.2
–0.1
0
0.1
0.2
0.1
1
10
100
N
OR
M
A
LIZE
D
C
LOS
E
D
-LOO
P
G
AI
N
(
d
B)
FREQUENCY (MHz)
CF = 3.3pF
CF = 0pF
CF = 1pF
VS = 5V
G = +2
RF = 604
RL = 150
VOUT = 2V p-p
Figure 54. 0.1 dB Gain Flatness vs. CF, VS = 5 V,
ADA4891-1/ADA4891-2
DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation. The ADA4891-1/ADA4891-2 are
used to demonstrate this effect (see Figure 55 and Figure 56).
–10
–8
–6
–4
–2
0
2
4
6
8
0.1
1
10
100
M
AG
NI
T
UDE
(
d
B)
FREQUENCY (MHz)
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
08054-
032
Figure 55. Closed-Loop Frequency Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
OU
TP
U
T
V
O
LT
A
G
E
(m
V)
50ns/DIV
50mV/DIV
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
0
100
–100
08054-
034
Figure 56. 200 mV Step Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
These four methods minimize the output capacitive loading effect.
Reducing the output resistive load. This pushes the pole
further away and, therefore, improves the phase margin.
Increasing the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitive loads with less peaking.
Adding a parallel capacitor (CF) with RF, from IN to the
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by the
capacitive load and the output impedance of the amplifier.
See the Effect of RF on 0.1 dB Gain Flatness section for
more information.
Placing a small value resistor (RS) in series with the output
to isolate the load capacitor from the output stage of the
amplifier.
the peaking in the worst-case frequency response (gain of +1).
Using RS = 100 reduces the peaking by 3 dB, with the trade-off
that the closed-loop gain is reduced by 0.9 dB due to attenuation
at the output. RS can be adjusted from 0 to 100 to maintain
an acceptable level of peaking and closed-loop gain, as shown in
M
AG
NI
T
UDE
(
d
B)
–10
–8
–6
–4
–2
0
2
4
6
8
0.1
1
10
100
FREQUENCY (MHz)
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
RS = 0Ω
RS = 100Ω
50
RL
RS
CL
OUT
VIN
200mV
STEP
08054-
033
Figure 57. Closed-Loop Frequency Response with Snub Resistor, CL = 6.8 pF
Figure 58 shows that the transient response is also much improved
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
RS = 100Ω
08054-
035
50ns/DIV
50mV/DIV
OU
TP
U
T
V
O
LT
A
G
E
(m
V)
0
100
–100
Figure 58. 200 mV Step Response, CL = 6.8 pF, RS = 100
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