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參數(shù)資料
型號(hào)： ADA4897-1ARJZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP GP RR 230MHZ LN SOT23-6
標(biāo)準(zhǔn)包裝： 3,000
放大器類(lèi)型： 電壓反饋
電路數(shù)： 1
輸出類(lèi)型： 滿擺幅
轉(zhuǎn)換速率： 120 V/µs
-3db帶寬： 230MHz
電流 - 輸入偏壓： 11µA
電壓 - 輸入偏移： 28µV
電流 - 電源： 3mA
電流 - 輸出 / 通道： 80mA
電壓 - 電源，單路/雙路(±)： 3 V ~ 10 V，±1.5 V ~ 5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 帶卷 (TR)
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
Rev.
| Page 21 of 28
LOW NOISE, GAIN SELECTABLE AMPLIFIER
09
44
7-
1
0
+5V
2
1
8
3
RG1
75
–5V
4
V01
VIN
ADA4896-2
+5V
6
7
8
5
–5V
4
V02
ADA4896-2
D1
D2
S1B
S1A
S2B
S3B
D3
S2A
V1
V2
RF1
75
RF2
225
RL
USING S3B IS OPTIONAL
ADG633
RBALANCE
150
Figure 52. Using the ADA4896-2 and the ADG633 to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load
A gain selectable amplifier makes processing a wide range of
input signals possible. A traditional gain selectable amplifier
uses switches in the feedback loops connecting to the inverting
input. The switch resistances degrade the noise performance of
the amplifier, as well as adding significant capacitance on the
inverting input node. The noise and capacitance issues can be
especially bothersome when working with low noise amplifiers.
Also, the switch resistances contribute to nonlinear gain error,
which is undesirable.
Figure 52 presents an innovative switching technique used in
the gain selectable amplifier such that the 1 nV/Hz noise per-
formance of the ADA4896-2 is preserved while the nonlinear
gain error is much reduced. With this technique, the user can
also choose switches with minimal capacitance to optimize the
bandwidth of the circuit.
In the circuit shown in Figure 52, the switches are implemented
with the ADG633 and are configured such that either S1A and
S2A are on, or S1B and S2B are on. In this example, when the
S1A and S2A switches are on, the first stage amplifier gain is +4.
When the S1B and S2B switches are on, the first stage amplifier
gain is +2. The first set of switches of the ADG633 is placed on
the output side of the feedback loop, and the second set of switches
is used to sample at a point (V1 or V2) where switch resistances
and nonlinear resistances do not matter. In this way, the gain
error can be reduced while preserving the noise performance
of the ADA4896-2.
Note that the input bias current of the output buffer can cause
problems with the impedance of the S2A and S2B sampling
switches. Both sampling switches are not only nonlinear with
voltage but with temperature as well. If this is an issue, place the
unused switch of the ADG633 (S3B) in the feedback path of the
output buffer to balance the bias currents (see Figure 52).
In addition, the bias current of the input amplifier causes
an offset at the output that varies based on the gain setting.
Because the input amplifier and the output buffer are mono-
lithic, the relative matching of their bias currents can be used
to cancel out the varying offset. Placing a resistor equal to the
difference between RF2 and RF1 in series with Switch S2A results
in a more constant offset voltage.
The following derivation shows that sampling at V1 yields the
desired signal gain without gain error. RS denotes the switch
resistance. V2 can be derived using the same method.
+
×
=
G1
S1
F1
IN
01
R
V
1
(7)
+
×
=
S1
G1
F1
G1
F1
01
R
V
V1
(8)
Substituting Equation 1 into Equation 2, the following
derivation is obtained.
+
×
=
G1
F1
IN
R
V
V1
1
(9)
Note that if V01 yields the desired signal gain without gain
error, the buffered output V02 will also be free from gain
error. Figure 53 shows the normalized frequency response of
the circuit at V02.
–30
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
6
N
O
R
M
A
L
IZ
E
D
C
L
OS
E
D
-L
OOP
GA
IN
(
d
B
)
FREQUENCY (MHz)
VS = ±5V
VIN = 100mV p-p
RL = 1k
G = +2
G = +4
0.1
1
10
100
500
09
44
7-
0
64
Figure 53. Frequency Response of V02/VIN
B
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