參數(shù)資料
型號(hào): ADA4898-2YRDZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大小: 0K
描述: IC OPAMP VF 65MHZ DL LN 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 電壓反饋
電路數(shù): 1
轉(zhuǎn)換速率: 55 V/µs
-3db帶寬: 65MHz
電流 - 輸入偏壓: 100nA
電壓 - 輸入偏移: 20µV
電流 - 電源: 7.9mA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): ±4.5 V ~ 16.5 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm Width)裸露焊盤
供應(yīng)商設(shè)備封裝: 8-SOIC-EP
包裝: 帶卷 (TR)
Data Sheet
ADA4898-1/ADA4898-2
Rev. D | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
36 V
Power Dissipation
Differential Mode Input Voltage
±1.5 V
Common-Mode Input Voltage
±11.4 V
Storage Temperature Range
65°C to +150°C
Operating Temperature Range
40°C to +105°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Table 4.
Package Type
θJA
θJC
Unit
Single 8-Lead SOIC_N_EP on a 4-Layer Board
47
29
°C/W
Dual 8-Lead SOIC_N_EP on a 4-Layer Board
42
29
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4898 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4898. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive depends
upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 4 shows the maximum power dissipation vs. the ambient
temperature for the single and dual 8-lead SOIC_N_EP on a
JEDEC standard 4-layer board, with its underside paddle
soldered to a pad that is thermally connected to a PCB plane. θJA
values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5.0
4.5
07037-
003
AMBIENT TEMPERATURE (°C)
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
0
20
40
60
80
100
10
30
50
70
90
–40
–20
–30
–10
ADA4898-2
ADA4898-1
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
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