參數(shù)資料
型號： ADA4930-2YCP-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/29頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADA4930-2YCP
標(biāo)準(zhǔn)包裝： 1
每 IC 通道數(shù)： 2 - 雙
放大器類型： 差分
板類型： 裸（未填充）
已供物品： 板
已用 IC / 零件： 24-LFCSP 封裝
ADA4930-1/ADA4930-2
Rev. A | Page 24 of 28
HIGH PERFORMANCE ADC DRIVING
The ADA4930-1/ADA4930-2 provide excellent performance in
3.3 V single-supply applications.
The circuit shown in Figure 59 is an example of the ADA4930-1
driving an AD9255, 14-bit, 80 MSPS ADC that is specified to
operate with a single 1.8 V supply. The performance of the ADC
is optimized when it is driven differentially, making the best use of
the signal swing available within the 1.8 V supply. The ADA4930-1
performs the single-ended-to-differential conversion, common-
mode level shifting, and buffering of the driving signal.
The ADA4930-1 is configured for a single-ended input to differential
output with a gain of 2 V/V. The 84.5 Ω termination resistor, in
parallel with the single-ended input impedance of 95.1 Ω, provides
a 50 Ω termination for the source. The additional 31.6 Ω (95 Ω
total) at the inverting input balances the parallel impedance of
the 50 Ω source and the termination resistor that drives the
noninverting input.
The VOCM pin is connected to the VCM output of the AD9255
and sets the output common mode of the ADA4930-1 at 1 V.
Note that a dc bias must be added to the signal source and its
Thevenin equivalent to the gain resistor on the inverting side
to ensure that the inputs of the ADA4930-1 are kept at or above
the specified minimum input common-mode voltage at all times.
The 0.5 V dc bias at the signal source and the 0.314 V dc bias on the
gain resistor at the inverting input set the inputs of the ADA4930-1
to ~0.48 V dc. With 1 V p-p maximum signal swing at the input,
the ADA4930-1 inputs swing between 0.36 V and 0.6 V.
For a common-mode voltage of 1 V, each ADA4930-1 output
swings between 0.501 V and 1.498 V, providing a 1.994 V p-p
differential output.
A third-order, 40 MHz, low-pass filter between the ADA4930-1
and the AD9255 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
The circuit shown in Figure 60 is an example of of an
ADA4930-2 driving of an AD9640, a 14-bit, 80 MSPS
ADC that is specified to operate with a single 1.8 V supply.
The performance of the ADC is optimized when it is driven
differentially, making the best use of the signal swing available
within the 1.8 V supply. The ADA4930-2 performs the single-
ended-to-differential conversion, common-mode level shifting,
and buffering of the driving signal.
The ADA4930-2 is configured for a single-ended input to differential
output with a gain of 2 V/V. The 88.5 Ω termination resistor, in
parallel with the single-ended input impedance of 114.75 Ω,
provides a 50 Ω termination for the source. The increased gain
resistance at the inverting input balances the 50 Ω source resistance
and the termination resistor that drives the noninverting input.
The VOCM pin is connected to the CML output of the AD9640 and
sets the output common mode of the ADA4930-2 at 1 V.
The 739 Ω resistors between each input and the 3.3 V supply
provide the necessary dc bias to guarantee compliance with the
input common-mode range of the ADA4930-2.
For a common-mode voltage of 1 V, each ADA4930-2 output
swings between 0.501 V and 1.498 V, providing a 1.994 V p-p
differential output.
A third-order, 40 MHz, low-pass filter between the ADA4930-2
and the AD9640 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
1.8V
DRVDD
AVDD
VIN–
VIN+
AD9255
AGND
VCM
D11 TO
D0
90pF
30pF
168nH
33
50
VIN
1V p-p
95
0.314V
63.4
VOCM
3.3V
ADA4930-1
+
0.5V
84.5
301
09
20
9-
15
7
Figure 59. Driving an AD9255, 14-Bit, 80 MSPS ADC
1.8V
DRVDD
AVDD
VIN–
VIN+
AD9640
AGND
CML
D11 TO
D0
90pF
30pF
168nH
50
VIN
1V p-p
96.2
64.2
739
VOCM
3.3V
ADA4930-2
+
88.5
301
09
20
9-
1
58
Figure 60. Driving an AD9640, 14-Bit, 80 MSPS ADC
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