參數(shù)資料
型號: ADAU1361BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 8/80頁
文件大?。?/td> 0K
描述: IC CODEC 24B PLL 32LFCSP
標準包裝: 5,000
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
電壓 - 電源,模擬: 1.8 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.8 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
ADAU1361
Rev. C | Page 16 of 80
Pin No.
Mnemonic
Type1
Description
19
RHP
A_OUT
Right Headphone Output. Biased at AVDD/2.
20
LHP
A_OUT
Left Headphone Output. Biased at AVDD/2.
21
MONOOUT
A_OUT
Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono
output.
22
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
23
AVDD
PWR
1.8 V to 3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator.
This pin should be decoupled locally to AGND with a 100 nF capacitor.
24
DVDDOUT
PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
25
DGND
PWR
Digital Ground. The AGND and DGND pins can be tied together on a common ground plane.
DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF
capacitors.
26
ADC_SDATA
D_OUT
ADC Serial Output Data.
27
DAC_SDATA
D_IN
DAC Serial Input Data.
28
BCLK
D_IO
Serial Data Port Bit Clock.
29
LRCLK
D_IO
Serial Data Port Frame Clock.
30
ADDR1/CDATA
D_IN
I2C Address Bit 1 (ADDR1).
SPI Data Input (CDATA).
31
SDA/COUT
D_IO
I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to
this pin should have a 2 kΩ pull-up resistor.
SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is
three-state when an SPI read is not active.
32
SCL/CCLK
D_IN
I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line
connected to this pin should have a 2 kΩ pull-up resistor.
SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions.
EP
Exposed Pad
Exposed Pad. The exposed pad is connected internally to the ADAU1361 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is recommended
that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for
more information.
1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, D_OUT = digital output, PWR = power.
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