參數(shù)資料
型號(hào)： ADAU1381BCBZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 17/84頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO LN 30WLCSP
標(biāo)準(zhǔn)包裝： 5,000
類型： 立體聲音頻
數(shù)據(jù)接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 97 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 96.5 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 30-UFBGA，WLCSP
供應(yīng)商設(shè)備封裝： 30-WLCSP（3.4x2.64）
包裝： 帶卷 (TR)
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 24 of 84
THEORY OF OPERATION
The ADAU1381 is a low power audio codec with an integrated,
fixed-function audio processing sound engine. It is an all-in-one
package that offers high quality audio, low power, small size, and
many advanced features. The stereo ADC and stereo DAC each
have a dynamic range (DNR) performance of at least 96.5 dB and
a total harmonic distortion plus noise (THD + N) performance
of at least 90 dB. The serial data port is compatible with I2S, left-
justified, right-justified, and TDM modes for interfacing to digital
audio data. The operating voltage range is 1.8 V to 3.65 V, with
an on-board regulator generating the internal digital supply voltage.
The record path includes very flexible input configurations that
can accept differential or single-ended analog microphone inputs
as well as two stereo digital microphone inputs. There is also a
beep input pin (BEEP) dedicated to analog beep signals that are
common in digital still camera applications. A microphone bias
pin that can power electrets-type microphones is also available.
Each input signal has its own programmable gain amplifier (PGA)
for input volume adjustment. An automatic level control (ALC)
is built into the sound engine to maintain a constant input re-
cording volume.
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at selectable 64× or 128× oversampling rates. The
base sampling rate of the converters is set by the input clock rate
and can be further scaled with the converter control register
settings. The converters can operate at sampling frequencies
from 8 kHz to 96 kHz. The ADCs and DACs also include very
fine-step digital volume controls.
The playback path allows input signals and DAC outputs to be
mixed into speaker and/or line outputs. The speaker driver is
capable of driving 400 mW into an 8 Ω load.
The fixed-function sound engine contains a digital audio
processing flow optimized for digital still camera stereo audio
processing. However, the flexibility offered by the built-in
sound engine allows this codec to be used for a wide variety of
low power applications. Signal processing blocks included in the
sound engine include the following:
Wind noise detection and autofiltering
Dual-band compression with programmable crossover,
compression curves, and timing
Programmable multiband equalizer
Configurable notch filter
Enhanced stereo capture algorithm
Automatic level control
Digital volume control
Multiplexers for signal routing
The ADAU1381 can generate its internal clocks from a wide
range of input clocks by using the on-board fractional PLL.
The PLL accepts inputs from 11 MHz to 20 MHz.
The ADAU1381 is provided in a small, 32-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP) with an exposed bottom
pad, or a 30-ball (6 × 5 bump), 3.4 mm × 2.64 mm wafer level
chip scale package (WLCSP).
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