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參數(shù)資料
| 型號： | ADAU1592ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO PWR 48LFCSP |
| 標準包裝： | 750 |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 24W x 2 @ 4 歐姆 |
| 電源電壓： | 9 V ~ 18 V |
| 特點： | 消除爆音，靜音，短路和熱保護，待機 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
ADAU1592
Rev. A | Page 19 of 24
To shut down the power supplies to save power, it is highly
recommended to mute the amplifier before shutting down any
of the supplies. To achieve this, first pull down MUTE, then
shut down the power supplies in the following order: PVDD,
DVDD, and then AVDD. Where AVDD and DVDD are
generated from a single source, shut down PVDD before
shutting down DVDD and AVDD, and after issuing MUTE.
DC OFFSET AND POP NOISE
This section describes the cause of dc offset and pop noise
during turn-on/turn-off. The turn-on/turn-off pop in amplifiers
depends mainly on the dc offset, therefore, care must be taken
to reduce the dc offset at the output.
The first stage of the ADAU1592 has an inverting PGA amplifier,
as shown in Figure 48.
0
67
49
-0
48
CHANGES WITH PGA SETTING
RFB
TO NEXT STAGE
AINx
VREF
CREF
RIN
RSOURCE
VMIS
CIN
Figure 48. Input Equivalent Circuit
where:
RIN = 20 kΩ, fixed internally.
RFB is the gain feedback resistor (value depends on the PGA
setting).
RSOURCE is the source resistance.
CIN is the input coupling capacitor (2.2 μF typical).
CREF is the filter capacitor for VREF.
VREF is the analog reference voltage (AVDD/2 typical).
VMIS is the dc offset due to mismatch in the op amp.
As shown in Figure 48, the dc offset at the output can be due to
VMIS (the dc offset from mismatch in the op amp) and due to
leakage current of the CIN capacitor.
Normally, the offset due to leakage current in the CIN is less and
can be ignored compared to VMIS. The VMIS is mainly responsi-
ble for the dc offset at the output. The ADAU1592 uses special
self-calibration or a dc offset trim circuit, which controls the dc
offset (due to VMIS) to within ±3 mV. The VMIS can vary for each
part as well as for voltage and temperature. The trim circuit
ensures that the offset is limited within specified limits and
provides virtually pop-free operation every time the part is
turned on. However, care must be taken while unmuting or
during the power-up sequence.
During the initial power-up, CIN and CREF are charging to
AVDD/2 and, during this time, there can be dc offset at the
output (see Figure 48). This depends on the PGA gain setting.
The dc offset is multiplied by the PGA gain setting. If the
amplifier is kept in mute during this charging and self-trimming
event for the recommended tWAIT time, the dc offset at the
output remains within ±3 mV. For more details on tWAIT, refer to
the Power-Up/Power-Down Sequence section.
The amount of pop at the turn-on depends on tWAIT, which in
turn depends on the values of CREF and CIN. The following
section describes how to select the value for the CREF and CIN.
SELECTING VALUES FOR CREF AND CIN
CREF is the capacitor used for filtering the noise from AVDD on
VREF. VREF is used for the biasing of the internal analog amplifier
as well as the modulator. Therefore, care must be taken to ensure
that the recommended minimum value is used. The minimum
recommended value for CREF is 4.7 μF.
CIN is the input coupling capacitor and is used to decouple the
inputs from the external dc. The CIN value determines the low
corner frequency of the amplifier. It can be determined from
the following equation:
IN
LOW
C
R
f
×
π
×
=
2
1
where:
fLOW is the low corner frequency (3 dB).
RIN is the input resistance (20 kΩ).
CIN is the input coupling capacitor.
Note that RIN = 20 kΩ and RSOURCE < 1 kΩ. If RSOURCE is sizable
with respect to RIN, it also must be taken into account in
calculation.
From the preceding equation, fLOW can be found for the desired
frequency response.
The recommended value for CIN is 2.2 μF, giving fLOW = 3.6 Hz,
and should keep 20 Hz roll-off within 0.5 dB.
However, if a higher than recommended CIN value is used for
better low frequency response, care must be taken to ensure that
Sequence section for more details.
MONO MODE
The ADAU1592 mono mode can be enabled by pulling MO/ST
(Pin 11) to logic high. In this mode, the left channel input and
modulator are active and feed PWM data to both the left and
right power stages. However, the respective power FETs need to
be connected externally for higher current capability. That is,
connect OUTL+ with OUTR+ and OUTL with OUTR. The
mono mode gives the capability to drive lower impedance loads
without invoking current limit. However, the output power is
limited by PVDD and temperature limits. See the typical applica-
tion schematic in Figure 50 for details.
POWER SUPPLY DECOUPLING
Because Class-D amplifiers utilize high frequency switching,
care must be taken for power supply decoupling.
For reliable operation, using 100 nF ceramic surface-mount
capacitors for the PVDD and PGND pins is recommended. A
minimum of two capacitors is needed: one between Pin 45/Pin 46
(PVDD) and Pin 47/Pin48 (PGND), the other between Pin 39/
Pin 40 (PVDD) and Pin 37/Pin 38 (PGND). In addition, these
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