- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378281 > ADC10062 (National Semiconductor Corporation) 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold PDF資料下載
參數(shù)資料
| 型號： | ADC10062 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 10位600納秒的A / D輸入多路復用器和轉(zhuǎn)換器采樣/保持 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 333K |
| 代理商： | ADC10062 |
Functional Description
(Continued)
total reference voltage across it. Tap points across these re-
sistors can be connected, in groups of sixteen, to the sixteen
comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
and V
. Six comparators com-
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input volt-
age. This estimate is then used to control the multiplexer that
connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input volt-
age. Only the sixteen comparators on the right and the six on
the left are necessary to perform the initial six-bit flash con-
version, instead of the 64 comparators that would be re-
quired using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Lad-
der tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator deter-
mines that V
is between 11/16 and 13/16 of V
. The es-
timator decoder will instruct the comparator MUX to connect
the 16 comparators to the taps on the MSB ladder between
10/16 and 14/16 of V
REF
. The 16 comparators will then per-
form the first flash conversion. Note that since the compara-
tors are connected to ladder voltages that extend beyond the
range indicated by the estimator circuit, errors in the estima-
tor as large as 1/16 of the reference voltage (64 LSBs) will
be corrected. This first flash conversion produces the six
most significant bits of data— four bits in the flash itself, and
2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash con-
version are reused for the second flash. Thus, the multistep
conversion technique used in the ADC10061, ADC10062,
and ADC10064 needs only a small fraction of the number of
comparators that would be required for a traditional flash
converter, and far fewer than would be used in a conven-
tional half-flash approach. This allows the ADC10061,
ADC10062, and ADC10064 to perform high-speed conver-
sions without excessive power drain.
Applications Information
1.0 MODES OF OPERATION
The ADC10061, ADC10062, and ADC10064 have two basic
digital interface modes. Figure 1 and Figure 2 are timing dia-
grams for the two modes. The ADC10062 and ADC10064
have input multiplexers that are controlled by the logic levels
on pins S
and S
when S/H goes low. Table 1is a truth table
showing how the input channnels are assigned.
DS011020-14
FIGURE 3. Block Diagram of the Multistep Converter Architecture
www.national.com
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC10062CIWM | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10064 | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10064CIWM | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10065 | ADC10065 10-Bit 65 MSPS 3V A/D Converter |
| ADC10065CIMT | ADC10065 10-Bit 65 MSPS 3V A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC10062BIJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| ADC10062CIWM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10062CIWM/NOPB | 功能描述:IC ADC 10BIT W/MUX 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10062CIWMX | 功能描述:IC ADC 10BIT W/MUX 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10062CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
發(fā)布緊急采購，3分鐘左右您將得到回復。