參數(shù)資料
型號： ADC1031
廠商： National Semiconductor Corporation
英文描述： Quadruple Bus Transceiver 16-SOIC 0 to 70
中文描述： ADC1031/ADC1034/ADC1038 10位串行I /辦公自動化/ D的模擬多路復用器和跟蹤器/保持功能
文件頁數(shù)： 10/18頁
文件大小： 349K
代理商： ADC1031
1.0 Pin Descriptions
C
CLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval.
The clock frequency applied to this input can be
between 700 kHz and 4 MHz.
S
CLK
The serial data clock input. The clock applied to
this input controls the rate at which the serial
data exchange occurs and the analog sampling
time available to acquire an analog input voltage.
The rising edge loads the information on the DI
pin into the multiplexer address shift register (ad-
dress register). This address controls which
channel of the analog input multiplexer (MUX) is
selected.
The falling edge shifts the data resulting from the
previous A/D conversion out on DO. CS and OE
enable or disable the above functions.
DI
The serial data input pin. The data applied to this
pin is shifted by S
CLK
into the multiplexer ad-
dress register. The first 3 bits of data (A0–A2)
are the MUX channel address (see the Multiplex-
er Address/Channel Assignment tables). The
fourth bit (R/L) determines the data format of the
conversion result in the conversion to be started.
When R/L is low the output data format is left-
justified; when high it is right-justified. When right-
justified, six leading ‘‘0’’s are output on DO be-
fore the MSB information; thus the complete con-
version result is shifted out in 16 clock periods.
DO
The data output pin. The A/D conversion result
(D0–D9) is output on this pin. This result can be
left- or right-justified depending on the value of
R/L bit shifted in on DI.
SARS
This pin is an output and indicates the status of
the internal successive approximation register
(SAR). When high, it signals that the A/D conver-
sion is in progress. This pin is set high after the
analog input sampling time (t
CA
) and remains
high for 41 C
CLK
periods. When SARS goes low,
the output shift register has been loaded with the
conversion result and another A/D conversion
sequence can be started.
CS
The chip select pin. When a low is applied to this
pin, the rising edge of S
CLK
shifts the data on DI
into the address register. In the ADC1031 this pin
also functions as the OE pin.
OE
The output enable pin. When OE and CS are
both low the falling edge of S
CLK
shifts out the
previous A/D conversion data on the DO pin.
CH0–
CH7
The analog inputs of the MUX. A channel input is
selected by the address information at the DI pin,
which is loaded on the rising edge of S
CLK
into
the address register.
Source impedances (R
S
) driving these inputs
should be kept below 1 k
X
. If R
S
is greater than
1 k
X
, the sampled data comparator will not have
enough time to acquire the correct value of the
applied input voltage.
The voltage applied to these inputs should not
exceed V
CC
or go below DGND or AGND by
more than 50 mV. Exceeding this range on an
unselected channel will corrupt the reading of a
selected channel.
V
REF
a
The positive analog voltage reference for the an-
alog inputs. In order to maintain accuracy the
voltage range of V
REF
(V
REF
e
V
REF
a
b
V
REF
b
) is 2.5 V
DC
to 5.0 V
DC
and the voltage at
V
REF
a
cannot exceed V
CC
a
50 mV. In the
ADC1031 V
REF
b
is always GND.
The negative voltage reference for the analog in-
puts. In order to maintain accuracy the voltage at
this pin must not go below DGND and AGND by
more than 50 mV or exceed 40% of V
CC
(for V
CC
e
5V, V
REF
b
(max)
e
2V). In the ADC1031
V
REF
b
is internally connected to the GND pin.
The power supply pin. The operating voltage
range of V
CC
is 4.75 V
DC
to 5.25 V
DC
. V
CC
should be bypassed with 10
m
F and 0.1
m
F ca-
pacitors to digital ground for proper operation of
the A/D converter.
V
REF
b
V
CC
DGND,
AGND
The digital and analog ground pins for the
ADC1034 and the ADC1038. In order to maintain
accuracy the voltage difference between these
two pins must not exceed 300 mV.
GND
The digital and analog ground pin for the
ADC1031.
2.0 Functional Description
2.1 DIGITAL INTERFACE
The ADC1034 and ADC1038 implement their serial inter-
face via seven digital control lines. There are two clock in-
puts for the ADC1034/ADC1038. The S
CLK
controls the
rate at which the serial data exchange occurs and the dura-
tion of the analog sampling time window. The C
CLK
controls
the conversion time and must be continuously enabled. A
low on CS enables the rising edge of S
CLK
to shift in the
serial multiplexer addressing data on the DI pin. The first
three bits of this data select the analog input channel for the
ADC1038 and the ADC1034 (see the Channel Addressing
Tables). The following bit, R/L, selects the output data for-
mat (right-justified or left-justified) for the conversion to be
started. With CS and OE low the DO pin is active (out of
TRI-STATE) and the falling edge of S
CLK
shifts out the data
from the previous analog conversion. When the first conver-
sion is started the data shifted out on DO is erroneous as it
depends on the state of the Parallel Load 16-Bit Shift Regis-
ter on power up, which is unpredictable.
The ADC1031 implements its serial interface with only four
control pins since it has only one analog input and comes in
an eight pin mini-dip package. The S
CLK
, C
CLK
, CS and DO
pins are available for the serial interface. The output data
format cannot be selected and defaults to a left-justified
format. The state of DO is controlled by CS only.
2.2 OUTPUT DATA FORMAT
When R/L is low the output data format is left-justified;
when high it is right-justified. When right-justified, six leading
‘‘0’’s are output on DO before the MSB, and the complete
conversion result is shifted out in 16 clock periods.
2.3.0 CS HIGH DURING CONVERSION
With a continuous S
CLK
input, CS must be used to synchro-
nize the serial data exchange. A valid CS is recognized if it
occurs at least 100 ns (t
SET-UP
) before the rising edge of
S
CLK
, thus causing data to be input on DI. If this does not
10
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