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參數(shù)資料
| 型號： | ADC10461CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 342K |
| 代理商： | ADC10461CIWM |
Functional Description
(Continued)
Each section of the MSB Ladder has
1
8
of the total reference
voltage across it, and each of the LSB resistors has 1/64 of
the total reference voltage across it. Tap points across these
resistors can be connected, in groups of sixteen, to the
sixteen comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
and V
. Six comparators com-
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input
voltage. This estimate is then used to control the multiplexer
that connects the MSB Ladder to the sixteen comparators on
the right. Note that the comparators on the left needn’t be
very accurate; they simply provide an estimate of the input
voltage. Only the sixteen comparators on the right and the
six on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen compara-
tors on the right. For example, assume that the estimator
determines that V
IN
is between 11/16 and 13/16 of V
REF
. The
estimator decoder will instruct the comparator MUX to con-
nect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 of V
. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion pro-
duces the six most significant bits of data—four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the multi-
step
conversion
technique
ADC10462, and ADC10464 needs only a small fraction of
the number of comparators that would be required for a
traditional flash converter, and far fewer than would be used
in a conventional half-flash approach. This allows the
ADC10461,
ADC10462,
and
high-speed conversions without excessive power drain.
used
in
the
ADC10461,
ADC10464
to
perform
Applications Information
1.0 MODES OF OPERATION
The ADC10461, ADC10462, and ADC10464 have two basic
digital interface modes. Figure 1 and Figure 2 are timing
diagrams for the two modes. The ADC10462 and ADC10464
have input multiplexers that are controlled by the logic levels
on pins S
0
and S
1
when S /H goes low. Tables 1, 2 are truth
tables showing how the input channnels are assigned.
Mode 1
In this mode, the S /H pin controls the start of conversion.
S /H is pulled low for a minimum of 250 ns. This causes the
comparators in the “coarse” flash converter to become ac-
01110813
FIGURE 3. Block Diagram of the Multistep Converter Architecture
A
www.national.com
10
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| ADC10462CIWM | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
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| ADC10461CIWMX | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10462CIWMX | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC10461CIWM/NOPB | 功能描述:IC ADC 10BIT 600 NS 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10461CIWMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10461CIWMX/NOPB | 制造商:Texas Instruments 功能描述:ADC Single 800ksps 10-bit Parallel 20-Pin SOIC W T/R |
| ADC10461CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| ADC10462 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
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