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參數(shù)資料
| 型號： | ADC10462CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 2-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 342K |
| 代理商： | ADC10462CIWM |
DC Electrical Characteristics
The following specifications apply for V
+
= +5V, V
REF(+)
= 5V V
REF()
= GND, and Speed Adjust pin unconnected unless other-
wise specified.
Boldface limits apply for T
A
= T
J
MIN
to T
MAX
all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
2.0
0.8
3.0
3.0
2.4
4.25
0.4
50
50
2
Units
(Limits)
V (min)
V (max)
μA (max)
μA (max)
V (min)
V (min)
V (max)
μA (max)
μA (max)
mA (max)
mA (max)
mA (max)
mA (max)
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
V
+
= 5.5V
V
+
= 4.5V
V
IN(1)
= 5V
V
IN(0)
0V
V
+
= 4.5V, I
OUT
= 360 μA
V
+
= 4.5V, I
OUT
= 10 μA
V
+
= 4.5V, I
OUT
= 1.6 mA
V
OUT
= 5V
V
OUT
= 0V
CS = S /H = RD = 0, R
SA
=
∞
CS = S /H = RD = 0, R
SA
= 18 k
CS = S /H = RD = 0, R
SA
=
∞
CS = S /H = RD = 0, R
SA
= 18 k
0.005
0.005
V
OUT(0)
I
OUT
Logical “0” Output Voltage
TRI-STATE
Output Current
0.1
0.1
1.0
1.0
30
30
DI
CC
DV
CC
Supply Current
AI
CC
AV
CC
Supply Current
45
AC Electrical Characteristics
The following specifications apply for V
+
= +5V, t
= t
= 20 ns, V
REF(+)
= 5V, V
= GND, and Speed Adjust pin uncon-
nected unless otherwise specified.
Boldface limits apply for T
A
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
t
CONV
Mode 1 Conversion Time
from Rising Edge of S /H
to Falling Edge of INT
Mode 2 Conversion Time
CIN,
CIWM Suffixes
R
SA
= 18k
CIN,
CIWM Suffixes
Mode 2, R
SA
= 18k
Mode 1; C
L
= 100 pF
600
375
750/
900
ns (max)
ns
t
CRD
850
530
30
1400
ns (max)
ns
ns (max)
t
ACC1
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Minimum Sample Time
TRI-STATE Control (Delay
from Rising Edge of RD
to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
Delay from End of Conversion
to Next Conversion
Multiplexer Control Setup Time
Multiplexer Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
60
t
ACC2
Mode 2; C
L
= 100 pF
900
t
CRD
+ 50
ns (max)
t
SH
t
1H
, t
0H
(Figure 1) ; (Note 9)
R
L
= 1k, C
L
= 10 pF
250
ns (max)
30
60
ns (max)
t
INTH
C
L
= 100 pF
25
50
50
ns (max)
ns (max)
t
P
t
MS
t
MH
C
VIN
C
OUT
C
IN
10
10
35
5
5
75
40
ns (max)
ns (max)
pF (max)
pF (max)
pF (max)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditons.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
A
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