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參數(shù)資料
| 型號： | ADC1061 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit High-Speed レP-Compatible A/D Converter with Track/Hold Function |
| 中文描述： | 10位高速レ的P -兼容的A / D轉(zhuǎn)換器與跟蹤/保持功能 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 320K |
| 代理商： | ADC1061 |
AC Electrical Characteristics
The following specifications apply for V
+
= +5V, t
r
= t
= 20 ns, V
= 5V, and V
REF()
= GND unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
1.2
Limit
(Note 8)
1.8
Units
(Limits)
μs (Max)
t
CONV
Conversion Time from Rising Edge
of S /H to Falling Edge of INT
Conversion Time for MODE 2
(RD Mode)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Minimum Sample Time
TRI-STATE Control (Delay from Rising
Edge of RD to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
Delay from INT to Output Valid
Delay from End of Conversion
to Next Conversion
Slew Rate for Correct
Track-and-Hold Operation
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
Mode 1
t
CRD
Mode 2
1.8
2.4
μs (Max)
t
ACC1
Mode 1; C
L
= 100 pF
20
50
ns (Max)
t
ACC2
Mode 2; C
L
= 100 pF
t
CRD
+ 50
ns (Max)
t
SH
t
1H
, t
0H
(Figure 1); (Note 9)
R
L
= 1k, C
L
= 10 pF
250
50
ns (Max)
ns (Max)
20
t
INTH
10
50
ns (Max)
t
ID
t
P
C
L
= 100 pF
20
10
50
20
ns (Max)
ns (Max)
SR
2.5
V/μs
C
VIN
C
OUT
C
IN
35
5
5
pF
pF
pF
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supply rails (V
<
V
or V
>
V
+
) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
,
θ
and the ambient temperature, T
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
T
A
)/
θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
=150C, and the typical thermal resistance (
θ
JA
) when board mounted is 47C/W for the plastic (N) package, 85C/W for the ceramic (J) package, and 65C/W
for the small outline (WM) package.
Note 5:
Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 6:
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7:
Typicals are at 25C and represent most likely parametric norm.
Note 8:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9:
Accuracy may degrade if t
SH
is shorter than the value specified.
TRI-STATE Test Circuits and Waveforms
DS010559-3
DS010559-4
www.national.com
4
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