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參數(shù)資料
| 型號： | ADC10732CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Plus Sign Serial I/O A/D Converters with Mux, |
| 中文描述： | 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大小： | 556K |
| 代理商： | ADC10732CIWM |
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Electrical Characteristics
(Continued)
The following specifications apply for V
+
= AV
+
= DV
+
= +5.0 V
DC
, V
+ = 2.5 V
, V
= GND, V
= 2.5V for Signed
Characteristics, V
= GND for Unsigned Characteristics and f
= 2.5 MHz unless otherwise specified.
Boldface limits ap-
ply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25C. (Notes 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 11)
Limits
(Note 12)
Units
(Limits)
AC CHARACTERISTICS
t
SCS
CS Set-Up Time, Set-Up Time from
Falling Edge of CS to Rising Edge of
Clock
14
30
ns(min)
(max)
(1 t
CLK
14 ns)
(1 t
CLK
30 ns)
t
SDI
DI Set-Up Time, Set-Up Time from
Data Valid on DI to Rising Edge of
Clock
DI Hold Time, Hold Time of DI Data
from Rising Edge of Clock to Data
not Valid on DI
DO Access Time from Rising Edge of
CLK When CS is “Low” during a
Conversion
DO or SARS Access Time from CS ,
Delay from Falling Edge of CS to
Data Valid on DO or SARS
Delay from Rising Edge of Clock to
Falling Edge of SARS when CS is
“Low”
DO Hold Time, Hold Time of Data on
DO after Falling Edge of Clock
DO Access Time from Clock, Delay
from Falling Edge of Clock to Valid
Data of DO
Delay from Rising Edge of CS to DO
or SARS TRI-STATE
Delay from Falling Edge of Clock to
Falling Edge of CS
CS “HIGH” Time for A/D Reset after
Reading of Conversion Result
ADC10731 Minimum CS “Low” Time
to Start a Conversion
Time from End of Conversion to CS
Going “Low”
Delay from Power-Down command to
10% of Operating Current
Delay from Power-Up Command to
Ready to Start a New Conversion
Capacitance of Logic Inputs
Capacitance of Logic Outputs
16
25
ns(min)
t
HDI
2
25
ns(min)
t
AT
30
50
ns(min)
t
AC
30
70
ns(max)
t
DSARS
100
200
ns(max)
t
HDO
20
35
ns(max)
t
AD
40
80
ns(max)
t
1H
, t
0H
40
50
ns(max)
t
DCS
20
30
ns(min)
t
CS(H)
1 CLK
1 CLK
cycle(min)
t
CS(L)
1 CLK
1 CLK
cycle(min)
t
SC
5 CLK
5 CLK
cycle(min)
t
PD
1
μs
t
PC
10
μs
C
IN
C
OUT
7
pF
pF
12
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2:
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de-
grade when the device is not operated under the listed test conditions.
Note 3:
All voltages are measured with respect to GND, unless otherwise specified.
Note 4:
When the input voltage (V
) at any pin exceeds the power supplies (V
<
GND or V
>
AV
+
or DV
+
), the current at that pln should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
,
θ
and the ambient temperature, T
. The maximum
allowable power dissipation at any temperature is P
D
= (T
Jmax
T
A
)/
θ
JA
or the number given In the Absolute Maximum Ratings, whichever is lower. For this device,
T
Jmax
= 150C. The typical thermal resistance (
θ
JA
) of these Paris when board mounted can be found in the following table:
www.national.com
7
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| ADC10734 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference |
| ADC10734CIMSA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Plus Sign Serial I/O A/D Converters with Mux, |
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