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參數(shù)資料
| 型號： | ADC10734 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 10-Bit Plus Sign Serial I/O A/D Converters with Mux,Sample/Hold and Reference(10位串行輸入/輸出帶MUX，采樣/保持和參考功能的A/D轉(zhuǎn)換器) |
| 中文描述： | 10位帶符號串行I /辦公自動(dòng)化/ D的復(fù)用器，采樣器/保持和參考（10位串行輸入/輸出帶復(fù)用，采樣/保持和參考功能的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 19/27頁 |
| 文件大小： | 556K |
| 代理商： | ADC10734 |
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Applications Hints
The ADC10731/2/4/8 use successive approximation to digi-
tize an analog input voltage. The DAC portion of theA/D con-
verters uses a capacitive array and a resistive ladder struc-
ture. The structure of the DAC allows a very simple switching
scheme to provide a versatile analog input multiplexer. This
structure also provides a sample/hold. The ADC10731/2/4/8
have a 2.5V CMOS bandgap reference. The serial digital I/O
interfaces to MICROWIRE and MICROWIRE+.
1.0 DIGITAL INTERFACE
There are two modes of operation. The fastest throughput
rate is obtained when CS is kept low during a conversion.
The timing diagrams in Figures 8, 9 show the operation of
the devices in this mode. CS must be taken high for at least
t
(1 CLK) between conversions. This is necessary to re-
set the internal logic. Figures 10, 11 show the operation of
the devices when CS is taken high while the ADC10731/2/
4/8 is converting. CS may be taken high during the conver-
sion and kept high indefinitely to delay the output data. This
mode simplifies the interface to other devices while the
ADC10731/2/4/8 is busy converting.
1.1 Getting Started with a Conversion
The ADC10731/2/4/8 need to be initialized after the power
supply voltage is applied. If CS is low when the supply volt-
age is applied then CS needs to be taken high for at least
t
(1 clock period). The data output after the first conver-
sion is not valid.
1.2 Software and Hardware Power Up/Down
These devices have the capability of software or hardware
power down. Figures 6, 7show the timing diagrams for hard-
ware and software power up/down. In the case of hardware
power down note that CS needs to be high for t
after PD
is taken low. When PD is high the device is powered down.
The total quiescent current, when powered down, is typically
200 μA with the clock at 2.5 MHz and 3 μA with the clock off.
The actual voltage level applied to a digital input will effect
the power consumption of the device during power down.
CMOS logic levels will give the least amount of current drain
(3 μA). TTL logic levels will increase the total current drain to
200 μA.
These devices have resistive reference ladders which draw
600 μA with a 2.5V reference voltage. The internal band gap
reference voltage shuts down when power down is acti-
vated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the de-
vice.
2.0 ARCHITECTURE
Before a conversion is started, during the analog input sam-
pling period, (t
), the sampled data comparator is zeroed. As
the comparator is being zeroed the channel assigned to be
the positive input is connected to the A/D’s input capacitor.
(The assignment procedure is explained in the Pin Descrip-
tions section.) This charges the input 32C capacitor of the
DAC to the positive analog input voltage. The switches
shown in the DAC portion of Figure 12 are set for this
zeroing/acquisition period. The voltage at the input and out-
put of the comparator are at equilibrium at this time. When
the conversion is started, the comparator feedback switches
are opened and the 32C input capacitor is then switched to
the assigned negative input voltage. When the comparator
feedback switch opens, a fixed amount of charge is trapped
on the common plates of the capacitors. The voltage at the
input of the comparator moves away from equilibrium when
the 32C capacitor is switched to the assigned negative input
voltage, causing the output of the comparator to go high (“1”)
or low (“0”). The SAR next goes through an algorithm, con-
trolled by the output state of the comparator, that redistrib-
utes the charge on the capacitor array by switching the volt-
age on one side of the capacitors in the array. The objective
of the SAR algorithm is to return the voltage at the input of
the comparator as close as possible to equilibrium.
The switch position information at the completion of the suc-
cessive approximation routine is a direct representation of
the digital output. This data is then available to be shifted on
the DO pin.
www.national.com
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