參數(shù)資料
型號： ADC10738CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 10-Bit Plus Sign Serial I/O A/D Converters with Mux,
中文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝： SOP-24
文件頁數(shù)： 23/27頁
文件大?。?/td> 556K
代理商： ADC10738CIWM
Applications Hints
(Continued)
3.4 Optional Adjustments
3.4.1 Zero Error
The zero error of the A/D converter relates to the location of
the first riser of the transfer function (see Figures 1, 2) and
can be measured by grounding the minus input and applying
a small magnitude voltage to the plus input. Zero error is the
difference between actual DC input voltage which is neces-
sary to just cause an output digital code transition from 000
0000 0000 to 000 0000 0001 and the ideal
1
2
LSB value (
1
2
LSB = 1.22 mV for V
REF
= + 2.500V).
The zero error of the A/D does not require adjustment. If the
minimum analog input voltage value, V
(Min), is not ground,
the effective “zero” voltage can be adjusted to a convenient
value. The converter can be made to output an all zeros digi-
tal code for this minimum input voltage by biasing any minus
input to V
(Min). This is useful for either the differential or
pseudo-differential input channel configurations.
3.4.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1
1
2
LSB down from the desired
analog full-scale voltage range and then adjusting the V
voltage (V
= V
REF+
– V
REF
) for a digital output code
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus
1
2
LSB is applied to
selected plus input and the zero reference voltage at the cor-
responding minus input should then be adjusted to just ob-
tain the 000 0000 0000 to 000 0000 0001 code transition.
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
where V
equals the high end of the analog input range,
V
equals the low end (the offset zero) of the analog
range. Both V
MAX
and V
are ground referred. The V
(V
= V
REF+
REF
) voltage is then adjusted to provide
a code change from 011 1111 1110 to 011 1111 1111. Note,
when using a pseudo-differential or differential multiplexer
mode where V
+ and V
are placed within the V
+
and
GND range, the individual values of V
and V
do not
matter, only the difference sets the analog input voltage
span. This completes the adjustment procedure.
3.5 The Input Sample and Hold
The ADC10731/2/4/8’s sample/hold capacitor is imple-
mented in the capacitor array. After the channel address is
loaded, the array is switched to sample the selected positive
analog input. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time (t
A
)
4.5 clock cycles.
This acquisition window of 4.5 clock cycles is available to al-
low the voltage on the capacitor array to settle to the positive
analog input voltage. Any change in the analog voltage on a
selected positive input before or after the acquisition window
will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is deter-
mined by the R
(3 k
) of the multiplexer switches, the
stray input capacitance C
(3.5 pF) and the total array (C
L
)
and stray (C
) capacitance (48 pF). For a large source re-
sistance the analog input can be modeled as an RC network
as shown in Figure 16 The values shown yield an acquisi-
tion time of about 1.1 μs for 10-bit unipolar or 10-bit plus sign
accuracy with a zero-to-full-scale change in the input volt-
age. External source resistance and capacitance will
lengthen the acquisition time and should be accounted for.
Slowing the clock will lengthen the acquisition time, thereby
allowing a larger external source resistance.
Absolute Using a 4.096V Span
DS011390-30
FIGURE 15. Different Reference Configurations
www.national.com
23
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