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參數(shù)資料
| 型號(hào)： | ADC10832 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Plus Sign Serial I/O A/D Converters with MUX, Sample/Hold and Reference |
| 中文描述： | 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 453K |
| 代理商： | ADC10832 |
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Pin Descriptions
CLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the mul-
tiplexer address shift register. This address con-
trols which channel of the analog input multi-
plexer (MUX) is selected. The falling edge shifts
the data resulting from the A/D conversion out
on DO. CS enables or disables the above func-
tions. The clock frequency applied to this input
can be between 5 kHz and 3 MHz.
DI
This is the serial data input pin. The data applied
to this pln is shifted by CLK into the multiplexer
address register. Tables I through III show the
multiplexer address assignment.
DO
The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the falling edge
of CLK on this pin.
CS
This is the chip select input pin. When a logic
low is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
PD
This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is pow-
ered up.
SARS
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address infor-
mation at the DI pin, which is loaded on the ris-
ing edge of CLK into the address register (see
Tables I–III).
The voltage applied to these inputs should not
exceed AV
a
or go below V
b
by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM
This pin is another analog input. When the ana-
log multiplexer is single ended this input serves
as the zero reference level for inputs CH0–CH7
(see Tables I-III). COM can serve as a ‘‘pseudo
ground’’ that has an input voltage range of AV
a
a
50 mV to V
b
b
50 mV. In most cases, COM
will be grounded. When the MUX is set in the
differential pairs mode, COM is not used and
may be grounded.
V
REF
a
This is the positive analog voltage reference in-
put. In order to malntaln accuracy, the voltage
range
V
REF
(V
REF
e
0.5 V
DC
to 5.0 V
DC
and the voltage at V
REF
a
cannot exceed AV
a
a
50 mV.
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND
b
50 mV or exceed AV
a
a
50 mV. V
REF
b
must always be less than
V
REF
a
.
V
REF
a
–V
REF
b
)
is
V
REF
b
AV
a
,
DV
a
These are the analog and digital positive power
supply pins. These pins should be tied to the
same power supply and bypassed separately.
The operating voltage range of AV
a
and DV
a
is 4.5 V
DC
to 5.5 V
DC
.
This is the negative analog supply pin. The oper-
ating voltage range of V
b
is
b
4.5V to
b
5.5V.
This supply pin needs to be bypassed with
0.1
m
F ceramic and 10
m
F tantalum capacitors
to the system analog ground.
V
b
DGND
This is the digital ground pin.
AGND
This is the analog ground pin.
19
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