參數(shù)資料
型號(hào)： ADC10838CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： 10-Bit Plus Sign Serial I/O A/D Converters with MUX, Sample/Hold and Reference
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： 0.300 INCH, PLASTIC, SOP-24
文件頁(yè)數(shù)： 20/30頁(yè)
文件大?。?/td> 453K
代理商： ADC10838CIWM
Applications Hints
The ADC10831/2/4/8 use successive approximation to
digitize an analog input voltage. The DAC portion of the A/D
converters uses a capacitive array and a resistive ladder
structure. The structure of the DAC allows a very simple
switching scheme to provide a versatile analog input multi-
plexer. This structure also provides a sample/hold. The
ADC10831/2/4/8 have a 2.5V CMOS bandgap reference.
The serial digital I/O interfaces to MICROWIRE and
MICROWIRE
a
.
1.0 DIGITAL INTERFACE
There are two modes of operation. The fastest throughput
rate is obtained when CS is kept low during a conversion.
The timing diagrams in Figures 7 and 8 show the operation
of the devices in this mode. CS must be taken high for at
least t
CS(H)
(1 CLK) between conversions. This is necessary
to reset the internal logic.Figures 9 and10 show the opera-
tion of the devices when CS is taken high while the
ADC10831/2/4/8 is converting. CS may be taken high dur-
ing the conversion and kept high indefinitely to delay the
output data. This mode simplifies the interface to other de-
vices while the ADC10831/2/4/8 is busy converting.
1.1 Getting Started with a Conversion
The ADC10831/2/4/8 need to be initialized after the power
supply voltage is applied. If CS is low when the supply volt-
age is applied then CS needs to be taken high for at least
t
CS(H)
(1 clock period). The data output after the first con-
version is not valid.
1.2 Software and Hardware Power Up/Down
These devices have the capability of software or hardware
power down. Figures 5 and 6 show the timing diagrams for
hardware and software power up/down. In the case of hard-
ware power down note that CS needs to be high for t
PC
after PD is taken low. When PD is high the device is pow-
ered down. The total quiescent current, when powered
down, is typically 200
m
A with the clock at 2.5 MHz and
3
m
A with the clock off. The actual voltage level applied to a
digital input will affect the power consumption of the
device during power down. CMOS logic levels will give the
least amount of current drain (3
m
A). TTL logic levels will
increase the total power down current drain to 300
m
A.
These devices have resistive reference ladders which draw
600
m
A with a 2.5V reference voltage. The internal band
gap reference voltage shuts down when power down is acti-
vated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the de-
vice.
2.0 ARCHITECTURE
Before a conversion is started, during the analog input sam-
pling period, (t
A
), the sampled data comparator is zeroed.
As the comparator is being zeroed the channel assigned to
be the positive input is connected to the A/D’s input capaci-
tor. (The assignment procedure is explained in the Pin De-
scriptions section.) This charges the input 32C capacitor of
the DAC to the positive analog input voltage. The switches
shown in the DAC portion ofFigure 11 are set for this zero-
ing/acquisition period. The voltage at the input and output
of the comparator are at equilibrium at this time. When the
conversion is started, the comparator feedback switches
are opened and the 32C input capacitor is then switched to
the assigned negative input voltage. When the comparator
feedback switch opens, a fixed amount of charge is trapped
on the common plates of the capacitors. The voltage at the
input of the comparator moves away from equilibrium when
the 32C capacitor is switched to the assigned negative input
voltage, causing the output of the comparator to go high
(‘‘1’’) or low (‘‘0’’). The SAR next goes through an algorithm,
controlled by the output state of the comparator, that redis-
tributes the charge on the capacitor array by switching the
voltage on one side of the capacitors in the array. The ob-
jective of the SAR algorithm is to return the voltage at the
input of the comparator as close as possible to equilibrium.
The switch position information at the completion of the
successive approximation routine is a direct representation
of the digital output. This data is then available to be shifted
on the D0 pin.
20
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