參數(shù)資料
型號(hào)： ADC1175-50
廠商： National Semiconductor Corporation
英文描述： 8-Bit, 50 MSPS, 125 mW A/D Converter
中文描述： 8位，50 MSPS的，125毫瓦的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 487K
代理商： ADC1175-50
Converter Electrical Characteristics
(Continued)
The following specifications apply for AV
= DV
= +5.0V
, OE = 0V, V
RT
= +2.6V, V
= 0.6V, C
= 20 pF,
f
CLK
= 20MHz at 50% duty cycle.
Boldface limits apply for T
A
= T
MIN
to T
MAX
;
all other limits T
A
= 25C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
Analog Input and Reference Characteristics
V
RB
Reference Bottom Self Bias
Voltage
V
RT
connected to V
RTS
V
RB
connected to V
RBS
V
RT
connected to V
RTS
,
V
RB
connected to V
RBS
V
RT
connected to V
RTS
,
V
RB
connected to V
SS
0.6
0.55
0.65
1.89
2.15
V(min)
V(max)
μAmin
μAmax
V
RTS
-
V
RBS
Self Bias Voltage Delta
2
2.3
V
V
RT
-
V
RB
Power Supply Characteristics
IA
DD
Analog Supply Current
ID
DD
Digital Supply Current
Reference Voltage Delta
2
1.0
2.8
V(min)
V(max)
DV
DD
= AV
DD
=5.25V
DV
DD
= AV
DD
=5.25V
DV
DD
AV
DD
=5.25V, f
CLK
= 20 MHz
DV
DD
AV
DD
=5.25V, f
CLK
= 30 MHz
DV
DD
= AV
DD
=5.25V, CLK Low
(Note 10)
DV
DD
= AV
DD
=5.25V, f
CLK
= 20 MHz
DV
DD
= AV
DD
=5.25V, f
CLK
= 30 MHz
9.5
2.5
12
13
mA
mA
mA
IAV
DD
+
IDV
DD
Total Operating Current
17
9.6
mA
Power Consumption
60
65
85
mW
mW
CLK, OE Digital Input Characteristics
V
IH
Logical High Input Voltage
V
IL
Logical Low Input Voltage
I
IH
Logical High Input Current
I
IL
Logic Low Input Current
C
IN
Logic Input Capacitance
Digital Output Characteristics
I
OH
High Level Output Current
I
OL
Low Level Output Current
I
OZH
,
I
OZL
AC Electrical Characteristics
f
C1
Maximum Conversion Rate
f
C2
Minimum Conversion Rate
t
OD
Output Delay
DV
DD
= AV
DD
= +5.25V
DV
DD
= AV
DD
= +5.25V
V
IH
= DV
DD
= AV
DD
= +5.25V
V
IL
= 0V, DV
DD
= AV
DD
= +5.25V
3.0
1.0
V (min)
V (max)
μA
μA
pF
5
5
5
DV
DD
= 4.75V, V
OH
= 2.4V
DV
DD
= 4.75V, V
OL
= 0.4V
DV
DD
= 5.25V
OE = DV
DD
, V
OL
= 0V or V
OH
= DV
DD
1.1
1.6
mA (min)
mA (max)
Tri-State
Leakage Current
±
20
μA
30
1
19
20
MHz(min)
MHz
ns(max)
Clock
Cycles
ns
ps rms
ns
ns
ns
CLK high to data valid
Pipline Delay (Latency)
2.5
t
DS
t
AJ
t
OH
t
EN
t
DIS
Sampling (Aperture) Delay
Aperture Jitter
Output Hold Time
OE Low to Data Valid
OE High to High Z State
CLK low to acquissition of data
3
30
10
11
15
7.5
7.3
7.2
6.5
47
46
45
40
CLK high to data invalid
Loaded as in Figure 2
Loaded as in Figure 2
f
IN
= 1.31 MHz, V
IN
= FS - 2 LSB
f
IN
= 4.43 MHz, V
IN
= FS - 2 LSB
f
IN
= 9.9 MHz, V
IN
= FS - 2 LSB
f
IN
= 4.43 MHz, f
CLK
= 30 MHz
f
IN
= 1.31 MHz, V
IN
= FS - 2 LSB
f
IN
= 4.43 MHz, V
IN
= FS - 2 LSB
f
IN
= 9.9 MHz, V
IN
= FS - 2 LSB
f
IN
= 4.43 MHz, f
CLK
= 30 MHz
ENOB
Effective Number of Bits
7.0
Bits (min)
SINAD
Signal-to- Noise & Distortion
43
dB(min)
A
www.national.com
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參數(shù)描述
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