參數(shù)資料
型號(hào)： ADC12010
廠商： National Semiconductor Corporation
英文描述： 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold
中文描述： 12位，10 MSPS的，160毫瓦的A / D轉(zhuǎn)換器，內(nèi)置采樣保持電路
文件頁(yè)數(shù)： 17/22頁(yè)
文件大?。?/td> 606K
代理商： ADC12010
Applications Information
(Continued)
TABLE 2. Input to Output Relationship—
Single-Ended Input
V
IN
+
V
IN
V
CM
V
CM
V
CM
V
CM
V
CM
Output
V
CM
V
REF
V
CM
V
REF
/2
V
CM
V
CM
+ V
REF
/2
V
CM
+ V
REF
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
1.3.1 Single-Ended Operation
Single-ended performance is lower than with differential in-
put signals. For this reason, single-ended operation is not
recommended. However, if single ended-operation is re-
quired, one of the analog inputs should be connected to the
d.c. common mode voltage of the driven input. The peak-to-
peak differential input signal should be twice the reference
voltage
to
maximize
SNR
(
Figure 2
b).
For example, set V
to 1.0V, bias V
to 1.0V and drive
V
+ with a signal range of 0V to 2.0V. Because very large
input signal swings can degrade distortion performance, bet-
ter performance with a single-ended input can be obtained
by reducing the reference voltage when maintaining a full-
range output.
Table 1
and
Table 2
indicate the input to output
relationship of the ADC12010.
and
SINAD
performance
1.3.2 Driving the Analog Input
The V
+ and the V
inputs of the ADC12010 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702 and the LMH6628 are good amplifiers for
driving the ADC12010.
The internal switching action at the analog inputs causes
energy to be output from the input pins.As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 100
series resistors at each of the signal
inputs with a 150 pF at each of the inputs, as can be seen in
Figure 5
and
Figure 6
. These components should be placed
close to the ADC because the input pins of the ADC is the
most sensitive part of the system and this is the last oppor-
tunity to filter the input.
Table 3
gives component values for
Figure 5
to convert individual input signals to a range of 2.5V
±
2.0V at each of the input pins of the ADC12010.
TABLE 3. Resistor Values for Circuit of
Figure 5
SIGNAL
RANGE
0 - 0.5V
0 - 1.0V
±
0.25V
±
0.5V
R1
R2
R3
R4
R5, R6
392
634
499
100
1540
1470
499
200
102
2490
499
100
115
1050
499
200
1000
499
1000
499
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
, should be in the
range of 0.5V to 4.0V and be of a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 0.5 Volts below the V
A
supply voltage. The nominal V
should generally be equal
to V
REF
/2, but V
RM
can be used as a V
CM
source as long as
V
CM
need not supply more than 10 μA of current.
2.0 DIGITAL INPUTS
The digital TTL/CMOS compatible inputs consist of CLK, OE
and PD.
2.1 CLK
The
CLK
signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 15 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90.
If the
CLK
is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 kSPS.
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12010 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 20% to 80%.
The clock line should be series terminated at the source end
in the characteristic impedance of that line if the clock line is
longer than
where t
is the rise time of the clock signal and t
is the
propagation rate along the line. For a Board of FR-4 mate-
rial, t
is typically about 150 ps/inch, or 60 ps/cm. This
resistor should be as close to the source as possible.
It might also be necessary to AC terminate the ADC end of
the clock line with a series RC to ground such that the
resistor value equals the characteristic impedance of the
clock line and the capacitor value is
where t
is again the propagation rate down the clock line,
L is the length of the line in inches and Z
is the character-
istic impedance of the clock line. A.C. termination should be
near the ADC clock pin but beyond that pin as seen from the
clock source.
Take care to maintain a constant clock line impedance
throughout the length of the line. Refer to Application Note
AN-905 or AN-1113 for information on setting and determin-
ing characteristic impedance.
A
www.national.com
17
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