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參數(shù)資料
| 型號： | ADC12010EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold |
| 中文描述： | 12位，10 MSPS的，160毫瓦的A / D轉(zhuǎn)換器，內(nèi)置采樣保持電路 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 606K |
| 代理商： | ADC12010EVAL |
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word. Output levels are TTL/CMOS compatible.
ANALOG POWER
5, 6, 29
V
A
Positive analog supply pins. These pins should be connected
to a quiet +5V voltage source and be bypassed to AGND with
0.1 μF monolithic capacitors located within 1 cm of these
power pins, and with a 10 μF capacitor.
The ground return for the analog supply.
4, 7, 28
DIGITAL POWER
AGND
13
V
D
Positive digital supply pin. This pin should be connected to
the same quiet +5V source as is V
A
and bypassed to DGND
with a 0.1 μF monolithic capacitor in parallel with a 10 μF
capacitor, both located within 1 cm of the power pin.
The ground return for the digital supply.
Positive digital supply pin for the ADC12010’s output drivers.
This pin should be connected to a voltage source of +2.35V
to +5V and be bypassed to DR GND with a 0.1 μF monolithic
capacitor. If the supply for this pin is different from the supply
used for V
A
and V
D
, it should also be bypassed with a 10 μF
tantalum capacitor. V
DR
should never exceed the voltage on
V
D
. All bypass capacitors should be located within 1 cm of the
supply pin.
The ground return for the digital supply for the ADC12010’s
output drivers. This pin should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12010’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
9, 12
DGND
21
V
DR
20
DR GND
A
www.national.com
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