參數(shù)資料
型號(hào)： ADC12020
廠商： National Semiconductor Corporation
英文描述： NiCd Gas Gauge For High Discharge Rates (>5A), Small Pack Capacities (<2Ah) 16-SOIC 0 to 70
中文描述： 12位，20 MSPS的，185毫瓦的A / D轉(zhuǎn)換器，內(nèi)置采樣保持電路
文件頁(yè)數(shù)： 19/23頁(yè)
文件大?。?/td> 621K
代理商： ADC12020
Applications Information
(Continued)
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12020 will continue to convert whether
this pin is high or low, but the output can not be read while
the OE pin is high.
The OE pin should NOT be used to multiplex devices to-
gether to drive a common bus as this will result in excessive
capacitance on the data output pins, reducing SNR and
SINAD performance of the converter. See Section 3.0.
2.3 PD
The PD pin, when high, holds the ADC12020 in a power-
down mode to conserve power when the converter is not
being used. The power consumption 40 mW and the output
data pins are undefined in this mode. The data in the pipeline
is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32. These capaci-
tors loose their charge in the Power Down mode and must
be charged by on-chip circuitry before conversions can be
accurate.
3.0 OUTPUTS
The ADC12020 has 12 TTL/CMOS compatible Data Output
pins. Valid offset binary data is present at these outputs while
the OE and PD pins are low. While the t
time provides
information about output timing, a simple way to capture a
valid output is to latch the data on the falling edge of the
conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
DR
and DR GND. These large charging current
spikes can cause on-chip noise that can couple into the
analog circuitry, degrading dynamic performance. Adequate
power supply bypassing and careful attention to the ground
plane will reduce this problem. Additionally, bus capacitance
beyond the specified 25 pF/pin will cause t
OD
to increase,
making it difficult to properly latch the ADC output data. The
result could be an apparent reduction in dynamic perfor-
mance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ing buffers (74ACQ541, for example) between the ADC out-
puts and any other circuitry. Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 47
to 100
at the digital outputs, close to the
ADC pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could oth-
erwise result in performance degradation. See
Figure 4
.
While the ADC12010 will operate with V
voltages down to
1.8V, t
increases with reduced V
DR
. Be careful of external
timing when using reduced V
DR
.
20051713
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
A
www.national.com
19
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