參數(shù)資料
型號: ADC12030
廠商: National Semiconductor Corporation
元件分類: 串行ADC
英文描述: Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述: 自校準(zhǔn)12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持
文件頁數(shù): 8/41頁
文件大?。?/td> 1036K
代理商: ADC12030
DC and Logic Electrical Characteristics
(Continued)
The following specifications apply for V
+
= V
+ = V
+ = +5.0 V
, V
+ = +4.096 V
, V
= 0 V
DC
, 12-bit + sign conver-
sion mode, f
= f
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25
, source impedance for V
+ and V
25
, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
) acquisition time unless otherwise specified.
Boldface limits apply
for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
I
A
+
Positive Analog Supply Current
Awake
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
Awake
CS = HIGH, Powered Down
2.7
10
0.1
70
0.1
4.0
mA (max)
μA
μA
μA
μA
I
REF
Reference Input Current
AC Electrical Characteristics
The following specifications apply for V
+
= V
+ = V
+ = +5.0 V
, V
+ = +4.096 V
, V
= 0 V
, 12-bit + sign conver-
sion mode, t
= t
= 3 ns, f
= f
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
= 25
, source impedance for V
+ and V
25
,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
) acquisition time unless otherwise specified.
Bold-
face limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
ADC12H030/2/4/8
Limits
(Note 11)
8
ADC12030/2/4/8
Limits
(Note 11)
5
Units
(Limits)
f
CK
Conversion Clock
(CCLK) Frequency
Serial Data Clock
SCLK Frequency
Conversion Clock
Duty Cycle
Serial Data Clock
Duty Cycle
Conversion Time
10
1
10
0
MHz (max)
MHz (min)
MHz (max)
Hz (min)
% (min)
% (max)
% (min)
% (max)
(max)
μs (max)
(max)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
f
SK
8
5
40
60
40
60
40
60
40
60
t
C
12-Bit + Sign or 12-Bit
44(t
CK
)
44(t
CK
)
5.5
21(t
CK
)
2.625
6(t
CK
)
7(t
CK
)
0.75
0.875
10(t
CK
)
11(t
CK
)
1.25
1.375
18(t
CK
)
19(t
CK
)
2.25
2.375
34(t
CK
)
35(t
CK
)
4.25
4.375
44(t
CK
)
8.8
21(t
CK
)
4.2
6(t
CK
)
7(t
CK
)
1.2
1.4
10(t
CK
)
11(t
CK
)
2.0
2.2
18(t
CK
)
19(t
CK
)
3.6
3.8
34(t
CK
)
35(t
CK
)
6.8
7.0
8-Bit + Sign or 8-Bit
21(t
CK
)
t
A
Acquisition Time
(Note 19)
6 Cycles Programmed
6(t
CK
)
10 Cycles Programmed
10(t
CK
)
18 Cycles Programmed
18(t
CK
)
34 Cycles Programmed
34(t
CK
)
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