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參數資料
| 型號： | ADC12032CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數： | 4/41頁 |
| 文件大小： | 1036K |
| 代理商： | ADC12032CIWM |
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Pin Descriptions
(Continued)
exception of the first bit of data. When CS is
low continously, the first bit of the data is
clocked out on the rising edge of EOC (end
of conversion). When CS is toggled the fall-
ing edge of CS always clocks out the first bit
of data. CS should be brought low when
SCLK is low. The falling edge of CS resets a
conversion in progress and starts the se-
quence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely terminated. The
data in the output latches may be corrupted.
Therefore, when CS is brought back low
during a conversion in progress the data
output at that time should be ignored. CS
may also be left continuously low. In this
case it is imperative that the correct number
of SCLK pulses be applied to the ADC in or-
der to remain synchronous. After the ADC
supply power is applied it expects to see 13
clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is
the same as the digital output word length.
This word length can be modified by the
data shifted in on the DO pin. Table 5details
the data required.
This is the data output ready pin. This pin is
an active push/pull output. It is low when the
conversion result is being shifted out and
goes high to signal that all the data has
been shifted out.
Alogic low is required on this pin to program
any mode or change the ADC’s configura-
tion as listed in the Mode Programming
Table 5such as 12-bit conversion, 8-bit con-
version, Auto Cal, Auto Zero etc. When this
pin is high the ADC is placed in the read
data only mode. While in the read data only
mode, bringing CS low and pulsing SCLK
will only clock out on DO any data stored in
the ADCs output shift register. The data on
DI will be neglected. A new conversion will
not be started and the ADC will remain in
the mode and/or configuration previously
programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.
This is the power down pin. When PD is
high the A/D is powered down; when PD is
low the A/D is powered up. The A/D takes a
maximum of 250 μs to power up after the
command is given.
These are the analog inputs of the MUX. A
channel input is selected by the address in-
formation at the DI pin, which is loaded on
the rising edge of SCLK into the address
register (See Tables 2, 3, 4).
The voltage applied to these inputs should
not exceed V
+ or go below GND. Exceed-
ing this range on an unselected channel will
corrupt the reading of a selected channel.
This pin is another analog input pin. It is
used as a pseudo ground when the analog
multiplexer is single-ended.
DOR
CONV
PD
CH0–CH7
COM
MUXOUT1,
MUXOUT2
A/DIN1, /DIN2 These are the converter input pins. MUX-
OUT1 is usually tied to A/DIN1. MUXOUT2
is usually tied to A/DIN2. If external circuitry
is placed between MUXOUT1 and A/DIN1,
or MUXOUT2 and A/DIN2 it may be neces-
sary to protect these pins. The voltage at
these pins should not exceed V
A+
or go be-
low AGND (see Figure 5).
V
REF
+
This is the positive analog voltage reference
input. In order to maintain accuracy, the
voltage range of V
(V
REF
= V
REF
+
V
) is 1 V
to 5.0 V
DC
at V
+ cannot exceed V
+. See Figure 6
for recommended bypassing.
V
REF
The negative voltage reference input. In or-
der to maintain accuracy, the voltage at this
pin must not go below GND or exceed V
A
+.
(See Figure 6).
V
A
+, V
D
+
These are the analog and digital power sup-
ply pins. V
A+
and V
D+
are not connected to-
gether on the chip. These pins should be
tied to the same power supply and by-
passed separately (see Figure 6). The oper-
ating voltage range of V
A
+ and V
D
+ is
4.5 V
DC
to 5.5 V
DC
.
DGND
This is the digital ground pin (see Figure 6).
AGND
This is the analog ground pin (see Figure 6).
These
pins.
are
the
multiplexer
output
www.national.com
4
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