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參數(shù)資料
| 型號： | ADC12040 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 40 MSPS, 340 mW A/D Converter with Internal Sample-and-Hold |
| 中文描述： | 12位，40 MSPS的，340毫瓦的A / D轉(zhuǎn)換器，內(nèi)置采樣保持電路 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 519K |
| 代理商： | ADC12040 |
Functional Description
Operating on a single +5V supply, the ADC12040 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving
that pin.
The output word rate is the same as the clock frequency,
which can be between 100 kSPS and 50 MSPS (typical).
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by
the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 70 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12040:
4.75V
≤
V
A
≤
5.25V
V
D
= V
A
2.35V
≤
V
DR
≤
V
D
100 kHz
≤
f
CLK
≤
50 MHz
1.0V
≤
V
REF
≤
2.2V
1.1 ANALOG INPUTS
TheADC12040 has two analog signal inputs, V
+ and V
.
These two pins form a differential input pair. There is one
reference input pin, V
REF
.
1.2 REFERENCE PINS
TheADC12040 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of
1.0V to 2.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12040. Increasing the
reference voltage (and the input signal swing) beyond 2.2V
will degrade THD for a full-scale input. It is very important
that all grounds associated with the reference voltage and
the input signal make connection to the analog ground plane
at a single point to minimize the effects of noise currents in
the ground path.
The three Reference Bypass Pins (V
, V
and V
) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 μF capacitor. DO
NOT LOAD these pins.
1.3 SIGNAL INPUTS
The signal inputs are V
IN
+ and V
IN
. The input signal, V
IN
, is
defined as
V
IN
= (V
IN
+) – (V
IN
)
Figure 2
shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
/2. The input signals should re-
main between ground and 4V.
The Peaks of the individual input signals (V
IN
+ and V
IN
)
should each never exceed the voltage described as
V
IN
+, V
IN
= V
REF
/2 + V
CM
≤
4V (differential)
to maintain THD and SINAD performance.
The ADC12040 performs best with a differential input with
each input centered around V
. The peak-to-peak voltage
swing at both V
+ and V
should not exceed the value of
the reference voltage or the output data will be clipped. The
two input signals should be exactly 180 out of phase from
each other and of the same amplitude. For single frequency
inputs, angular errors result in a reduction of the effective full
scale input. For a complex waveform, however, angular
errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
E
FS
= dev
1.79
Where dev is the angular difference between the two signals
having a 180 relative phase relationship to each other (see
Figure 3
). Drive the analog inputs with a source impedance
less than 100
.
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, V
REF
, and be centered around V
CM
.
TABLE 1. Input to Output Relationship—
Differential Input
V
IN
+
V
IN
Output
V
CM
V
REF
/2
V
CM
V
REF
/4
V
CM
V
CM
+ V
REF
/2
V
CM
+ V
REF
/2
V
CM
+ V
REF
/2
V
CM
+ V
REF
/4
V
CM
V
CM
V
REF
/4
V
CM
V
RE/2F
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
20014811
FIGURE 2. Expected Input Signal Range
20014812
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level
A
www.national.com
14
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| ADC12040_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold |
| ADC12040CIVY | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12040CIVY/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12040CIVYX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12040CIVYX/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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