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參數(shù)資料
| 型號： | ADC12048EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
| 中文描述： | 12位帶符號216 kHz的8聲道采樣模擬到數(shù)字轉換器 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 635K |
| 代理商： | ADC12048EVAL |
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Digital Timing Characteristics
(Continued)
The following specifications apply to the ADC12048, 13-bit data bus width, V
A
+ = V
D
+ = 5V, f
CLK
= 12 MHz, t
f
= 3 ns and C
L
= 50 pF on data I/O lines
Symbol
Parameter
Conditions
Typical
(Note 10)
26
23
Limits
(Note 11)
44
32
Units
(Limit)
ns (max)
ns (max)
t
RDDATA
t
RDHOLD
t
RDRDY
Falling Edge of RD to Valid Data
Read Hold Time
Rising Edge of RD to Rising Edge of
RDY
Active Edge of WR to Rising Edge of
RDY
Active Edge of WR to Falling Edge of
STDBY
13-Bit Mode (BW Bit = “1”)
24
38
ns (max)
t
WRRDY
WMODE = “1”
42
65
ns (max)
t
STNDBY
WMODE = “0”. Writing the
Standby Command into the
Configuration Register
WMODE = “0”. Writing the
RESET Command into the
Configuration Register
WMODE = “0”. Writing the
RESET Command into the
Configuration Register
200
230
ns (max)
t
STDONE
Active Edge of WR to Rising Edge of
STDBY
30
45
ns (max)
t
STDRDY
Active Edge of WR to Falling Edge of
RDY
1.4
2.5
ms (max)
t
SYNC
Minimum SYNC Pulse Width
5
10
ns (min)
Notes on Specifications
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-
tions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
GND or V
IN
>
(V
A
+ or V
D
+)), the current at that pin should be limited to
30 mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4:
The maximum power dissipation must he derated at elevated temperatures and is dictated by T
Jmax
, (maximum junction temperature),
θ
JA
(package junc-
tion to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any temperature is P
Dmax
= (T
Jmax
T
A
)/
θ
JA
or
the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
= 150C, and the typical thermal resistance (
θ
JA
) of the ADC12048
in the V package, when board mounted, is 55C/W, and in the VF package, when board mounted, is 67.8C/W.
Note 5:
Human body model, 100 pF discharged through 1.5 k
resistor.
Note 6:
Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above
V
A
+ or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D
conversion can occur if these diodes are forward biased by more than 50 mV.As an example, if V
A
+ is 4.50 V
DC
, full-scale input voltage must be
≤
4.55 V
DC
to ensure
accurate conversions.
Note 7:
V
A
+ and V
D
+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+
pin to assure conversion/
comparison accuracy.
Refer to the Power Supply Considerations
section for a detailed discussion.
Note 8:
Accuracy is guaranteed when operating at
f
CLK
= 12 MHz.
Note 9:
With the test condition for V
REF
(V
REF
+ V
REF
) given as +4.096V, the 12-bit LSB is 1.000 mV.
Note 10:
Typicals are at T
A
= 25C and represent most likely parametric norm.
Note 11:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12:
Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
DS012387-4
A
www.national.com
8
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