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參數(shù)資料
| 型號： | ADC1205CCJ-1 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit Plus Sign mP Compatible A/D Converters |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 327K |
| 代理商： | ADC1205CCJ-1 |
Functional Description
(Continued)
TABLE II. Status Bit Locations and Meanings
(Continued)
Status
Bit
Location
Status
Bit
Condition to
Clear Status
Bit
Meaning
DB1
EOC
‘‘High’’ indicates that
the conversion is
completed and data is
transferred to the
output latch.
DB0
INT
‘‘High’’ indicates that
it is the end of the
conversion and the
data is ready to read
Data read or
status read
or status
write
3.0 INTERFACE
3.1 RESET OF INTERRUPT
INT goes low at the end of the conversion and indicates that
data is transferred to the output latch. By reading data, INT
will be reset to high on the leading edge of the first read (RD
going low). INT is also reset on the leading (falling) edge of
WR when starting a conversion.
3.2 READY OUT
To simplify the hardware connection to high speed micro-
processors, a READY OUT line is provided. This allows the
A-to-D to insert a wait state in the
m
P’s read cycle. The
equivalent circuit and the timing diagram for READY OUT is
shown in Figures 7 and 8.
TL/H/5676–9
FIGURE 7. READY OUT Equivalent Circuit
TL/H/5676–10
FIGURE 8. READY OUT Timing Diagram
3.3 RESETTING THE A/D
All the internal logic can be reset, which will abort any con-
version in process and reset the status bits. The reset func-
tion is achieved by performing a status write (CS, WR and
STATUS are low).
3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS
ADC1225
1. WR and RD can be tied together with CS low continu-
ously or strobed. The previous conversion’s data will be
available when the WR and RD are low as shown below.
One drawback is that, since the conversion is started on the
falling edge and the data read on the rising edge of WR/RD,
the first data access will have erroneous information de-
pending on the power-up state of the internal output latch-
es.
If the WR/RD strobe is longer than the conversion time,
INTR will never go low to signal the end of a conversion.
The conversion will be completed and the output latches will
be updated. In this case the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated.
TL/H/5676–24
FIGURE 9
10
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| ADC12062CIV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 1 MHz, 75 mW A/D Converter |
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