參數(shù)資料
型號(hào)： ADC12062BIV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 12-Bit, 1 MHz, 75 mW A/D Converter
中文描述： 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 9/20頁(yè)
文件大小： 355K
代理商： ADC12062BIV
Pin Descriptions
AV
CC
These are the two positive analog supply
inputs. They should always be connected
to the same voltage source, but are
brought out separately to allow for sepa-
rate bypass capacitors. Each supply pin
should be bypassed to AGND with a
0.1
m
F ceramic capacitor in parallel with a
10
m
F tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AV
CC
. It
should be bypassed to DGND2 with a
0.1
m
F ceramic capacitor in parallel with a
10
m
F tantalum capacitor.
These are the power supply ground pins.
There are separate analog and digital
ground pins for separate bypassing of the
analog and digital supplies. The ground
pins should be connected to a stable,
noise-free
system
ground.
ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
DV
CC
AGND,
DGND1,
DGND2
All
of
the
DB0–DB11
These are the TRI-STATE output pins, en-
abled by RD, CS, and OE.
V
IN1
, V
IN2
These are the analog input pins to the mul-
tiplexer. For accurate conversions, no in-
put pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above V
CC
.
This is the output of the on-board analog
input multiplexer.
MUX OUT
ADC IN
This is the direct input to the 12-bit sam-
pling A/D converter. For accurate conver-
sions, this pin should not be driven more
than 50 mV below AGND or 50 mV above
AV
CC
.
This pin selects the analog input that will
be connected to the ADC12062 during the
conversion. The input is selected based on
the state of S0 when EOC makes its high-
to-low transition. Low selects V
IN1
, high
selects V
IN2
.
S0
MODE
This pin should be tied to DV
CC
.
This is the active low Chip Select control
input. When low, this pin enables the RD,
S/H, and OE inputs. This pin can be tied
low.
CS
INT
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure 1), this output goes low when a
conversion has been completed and indi-
cates that the conversion result is avail-
able in the output latches. This output is
always high when RD is held low (Figure
2).
EOC
This is the End-of-Conversion control out-
put. This output is low during a conversion.
RD
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data ap-
pears on the data bus. This pin can be tied
low.
OE
This is the active high Output Enable con-
trol input. This pin can be thought of as an
inverted version of the RD input (see Fig-
ure 6). Data output pins DB0–DB11 are
TRI-STATE when OE is low. Data appears
on DB0–DB11 only when OE is high and
CS and RD are both low. This pin can be
tied high.
S/H
This is the Sample/Hold control input. The
analog input signal is held and a new con-
version is initiated by the falling edge of
this control input (when CS is low).
PD
This is the Power Down control input. This
pin should be held high for normal opera-
tion. When this pin is pulled low, the device
goes into a low power standby mode.
V
REF
a
(FORCE)
, These are the positive and negative volt-
V
REF
b
(FORCE)
age reference force inputs, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
V
REF
a
(SENSE)
, These are the positive and negative volt-
V
REF
b
(SENSE)
age reference sense pins, respectively.
See Section 4, REFERENCE INPUTS, for
more information.
V
REF
/16
This pin should be bypassed to AGND with
a 0.1
m
F ceramic capacitor.
This pin should be tied to DV
CC
.
TEST
9
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