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參數(shù)資料
| 型號： | ADC12062EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 1 MHz, 75 mW A/D Converter |
| 中文描述： | 12位，1兆赫，75毫瓦的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC12062EVAL |
Applications Information
(Continued)
Since the current flowing through the SENSE lines is essen-
tially zero, there is negligible voltage drop across R
S
and the
1 k
X
resistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bot-
tom) of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps’s non-inverting input, plus or minus
its input offset voltage. For this reason op amps with low
V
OS
, such as the LM627 or LM607, should be used for this
application. When used in this configuration, the ADC12062
typically has less than 0.5 LSB of offset and gain error with-
out any user adjustments.
The 0.1
m
F and 10
m
F capacitors on the force inputs pro-
vide high frequency decoupling of the reference ladder. The
500
X
force resistors isolate the op amps from this large
capacitive load. The 0.01
m
F/1 k
X
network provides zero
phase shift at high frequencies to ensure stability. Note that
the op amp supplies in this example must be
g
10V to
g
15V to meet the input/output voltage range requirements
of the LM627 and supply the sub-zero voltage to the
V
REF
b
(FORCE)
pin. The V
REF/16
output should be by-
passed to analog ground with a 0.1
m
F ceramic capacitor.
The reference inputs are fully differential and define the
zero to full-scale range of the input signal. They can be
configured to span up to 5V (V
REF
b
e
0V, V
REF
a
e
5V),
or they can be connected to different voltages (within the
0V to 5V limits) when other input spans are required. The
ADC12062 is tested at V
REF
b
(SENSE)
e
0V, V
REF
a
(SENSE)
e
4.096V. Reducing the reference voltage span to
less than 4V increases the sensitivity (reduces the LSB size)
of the converter; however noise performance degrades
when lower reference voltages are used. A plot of dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section.
If the converter will be used in an application where DC
accuracy is secondary to dynamic performance, then a sim-
pler reference circuit may suffice. The circuit shown in Fig-
ure 11 will introduce several LSBs of offset and gain error,
but INL, DNL, and all dynamic specifications will be unaf-
fected.
All bypass capacitors should be located as close to the
ADC12062 as possible to minimize noise on the reference
ladder. The V
REF/16
output should be bypassed to analog
ground with a 0.1
m
F ceramic capacitor.
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
g
0.1%, it makes an excellent reference for the ADC12062.
TL/H/11490–21
FIGURE 11. Using the V
REF
Force Pins Only
15
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|---|---|
| ADC1206S040 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz |
| ADC1206S040/DB | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADC DEMO BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADC1206S040-DB | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADC1206S040H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz |
| ADC1206S040H/C1,51 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 40MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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