參數(shù)資料
型號: ADC1206S040
廠商: NXP Semiconductors N.V.
中文描述: Demoboard description Optional accessories Adaptor Type B for HSDC EXTMOD01-DB Demo box content CDROM (datasheets, PCB layout-schematics, Quickstart guide) Extension module Data Acquisition for ADC with CMOS input mode (HSDC-EXTMOD01-DB) ADC1206S Demo board Photo, Data Acquisition for ADC with CMOS outputs mode (HSDC-EXTMOD01-DB), 3D HSDC-ACC07,
文件頁數(shù): 4/6頁
文件大?。?/td> 197K
代理商: ADC1206S040
1.4 Output signals (D0 to D11, IR)
The digital output signal is available in binary or 2’s complement format.
An optional clock connector is available to simplify the acquisition clock generation.
Table 3.
Output signals
Name
Function
View
B8
Array connector – ADC digital output (D0 to D11)
B5
IR test point – It indicates the out of range state of the
analog input signal
J2-B11 CLK2 connector – Optional clock for the data acquisition
OTC switch – Output format selection
S3
Binary
2’s complement
CEN switch – Output enable selection
S4
Active output
High impedance output
1.5 Input common mode (CMADC)
The input common mode can be set by the internal reference of the ADC or can be
adjusted manually with a potentiometer.
Table 4.
Input common mode voltage adjustment
Name
Function
View
Switch – Selection between internal and external
common mode
S1
Internal common
mode
External common
mode
P1
Potentiometer – External common mode adjustment
B4
CMADC test point – input common mode
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