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參數(shù)資料
| 型號： | ADC1207S080HW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 12 bits ADC, up to 80 MHz with direct-ultra high IF sampling |
| 封裝： | ADC1207S080HW/C1<SOT545-2 (HTQFP48)|<<http://www.nxp.com/packages/SOT545-2.html<1<Always Pb-free,;ADC1207S080HW/C1<SOT545-2 (HTQFP48)|<<http://www.nxp.com/packages/SOT545 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | ADC1207S080HW |
ADC1207S080_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 7 August 2008
9 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
[1]
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with V
CCD
) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with V
CCD
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with V
CCD
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[2]
Guaranteed by design.
[3]
The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to V
CCA.
Output data acquisition: the output data is available after the maximum delay of t
d(o)
.
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[4]
[5]
[6]
The total harmonic distortion is obtained with the addition of the first five harmonics.
[7]
The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
[8]
Intermodulation measured relative to either tone with analog input frequencies f
i
1 and f
i
2. The two input signals have the same
amplitude and the total amplitude of both signals provides full-scale to the converter (
6 dB below full-scale for each input signal). IMD3
is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio
of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
S/N
signal-to-noise ratio
f
i
= 21.4 MHz
f
i
= 93 MHz
f
i
= 175 MHz
f
i
= 21.4 MHz
f
i
= 93 MHz
f
i
= 175 MHz
f
i
= 93 MHz; 5 MHz
channel spacing;
B = 3.84 MHz
f
i
1 = 21 MHz;
f
i
2 = 22 MHz
f
i
1 = 91.5 MHz;
f
i
2 = 94.5 MHz
f
i
1 = 174 MHz;
f
i
2 = 176 MHz
f
i
1 = 21 MHz;
f
i
2 = 22 MHz
f
i
1 = 91.5 MHz;
f
i
2 = 93.5 MHz
f
i
1 = 174 MHz;
f
i
2 = 176 MHz
[7]
-
67.4
67.2
66.5
76
78
74
70
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dB
63
-
-
68
-
-
SFDR
spurious free dynamic
range
ACPR
adjacent channel power
ratio
IMD2
second-order
intermodulation
distortion
[8]
-
89
-
dBFS
-
86
-
dBFS
-
83
-
dBFS
IMD3
third-order
intermodulation
distortion
[8]
-
88
-
dBFS
-
82
-
dBFS
-
83
-
dBFS
Table 5.
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
i(IN)
V
i(INN)
=
0.5 dBFS; V
ref(fs)
= V
CCA
1.87 V; V
I(cm)
= V
CCA
1.95 V; typical values measured at
V
CCA
= V
CCD
= 5 V V
CCO
= 3.3 V T
amb
= 25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1207S080HW/C1,1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 80MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1207S080HW/C1,118 | 制造商:NXP Semiconductors 功能描述: |
| ADC1207S080HW/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC ADC 12BIT 80MHZ SGL RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1207S080HW/C1,518 | 制造商:NXP Semiconductors 功能描述:Cut Tape 制造商:NXP Semiconductors 功能描述:0 |
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