參數(shù)資料
型號(hào)： ADC12130CIN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16
封裝： DIP-16
文件頁(yè)數(shù)： 27/41頁(yè)
文件大?。?/td> 1085K
代理商： ADC12130CIN
Tables
(Continued)
TABLE 6. Status Register
Status Bit
Location
Status Bit
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
PU
PD
Cal
12 or 13
16 or 17
Sign
Justification
Test
Mode
Device Status
“High”
indicates
a Power
Down
Sequence
is in
progress
DO Output Format Status
“High”
indicates
a 16 or
17 bit
format
included.
When
“Low” the
sign bit is
not
included.
Function
“High”
indicates
a Power
Up
Sequence
is in
progress
“High”
indicates
an
Auto-Cal
Sequence
is in
progress
Not used
“High”
indicates
a 12 or
13 bit
format
“High”
indicates
that the
sign bit is
When
“High” the
conversion
result will
be output
MSB first.
When “Low”
the result
will be
output LSB
first.
When
“High”
the
device is
in test
mode.
When
“Low” the
device is
in user
mode.
Application Hints
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in Figure 7shows a typical sequence of events
after the power is applied to the ADC12130/2/8:
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word, is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data out-
put at this time is again status information. To keep noise
from corrupting the A/D conversion, status can not be read
during a conversion. If CS is strobed and is brought low dur-
ing a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
theA/D controller can keep track in software of when it would
be appropriate to comnmunicate to the A/D again. Once it
has been determined that the A/D has completed a conver-
sion, another instruction can be transmitted to the A/D. The
data from this conversion can be accessed when the next in-
struction is issued to the A/D.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. The Data Out Format sets the number of SCLK
cycles required in the next I/O cycle. A 12-bit no sign format
will require 12 SCLKs to be transmitted; a 12-bit plus sign
format will require 13 SCLKs to be transmitted, etc. Not do-
ing so will desynchronize the serial communication to the
A/D. (See Section 1.3.)
1.2 Changing Configuration
The configuration of theADC12130/2/8 on power up defaults
to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10
CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the acquisition time
and turning the sign bit on and off requires an 8-bit instruc-
tion to be issued to the ADC. This instruction will not start a
conversion. The instructions that select a multiplexer ad-
dress and format the output data do start a conversion. Fig-
ure 8 describes an example of changing the configuration of
the ADC12130/2/8.
During I/O sequence 1, the instruction on DI configures the
ADC12130/2/8 to do a conversion with 12-bit +sign resolu-
tion. Notice that when the 6 CCLK Acquisition and Data Out
without Sign instructions are issued to the ADC, I/O se-
quences 2 and 3, a new conversion is not started. The data
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modi-
fication timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.
Table 4 describes the actual data necessary to be input to
the ADC to accomplish this configuration modification. The
next instruction, shown in Figure 8 issued to the A/D starts
conversion N+1 with 16-bit format with 12 bits of resolution
formatted MSB first. Again the data output during this I/O
cycle is the data from conversion N.
The number of SCLKs applied to the A/D during any conver-
sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se-
quence. The various formats and resolutions available are
shown in Table 1 In Figure 8 since 16-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 16. In the follow-
ing I/O sequence the format changes to 12-bit without sign
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
DS012079-32
FIGURE 7. Typical Power Supply Power Up Sequence
A
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27
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