參數(shù)資料
型號(hào)： ADC12138CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 1.2UF/100VDC METAL POLY CAP
中文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 11/41頁(yè)
文件大?。?/td> 1085K
代理商： ADC12138CIWM
AC Electrical Characteristics
(Continued)
Note 7:
Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
A
+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
A
+ or below GND by more than 50 mV. As an example, if V
A
+ is 4.5 V
DC
, full-scale input voltage must be
≤
4.55
V
DC
to ensure accurate conversions.
Note 8:
To guarantee accuracy, it is required that the V
A
+ and V
D
+ be connected together to the same power supply with separate bypass capacitors at each V
+
pin.
Note 9:
With the test condition for V
REF
(V
REF
+ V
REF
) given as +4.096V, the 12-bit LSB is 1.0 mV. For V
REF
= 2.5V, the 12-bit LSB is 610 μV.
Note 10:
Typicals are at T
J
= T
A
= 25C and represent most likely parametric norm.
Note 11:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12:
Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13:
Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-
tween 1 to 0 and 0 to +1 (see Figure 4).
Note 14:
Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15:
The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16:
Channel leakage current is measured after the channel selection.
Note 17:
Timing specifications are tested at the TTL logic levels, V
OL
= 0.4V for a falling edge and V
OL
= 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18:
The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19:
If SCLK and CCLK are driven from the same clock source, then t
A
is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20:
The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
DS012079-4
DS012079-5
FIGURE 1. Transfer Characteristic
A
www.national.com
11
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