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參數(shù)資料
| 型號： | ADC1215S080HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 12-bit ADC 80 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1215S080HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-6.html<1<Always Pb-free,;ADC1215S080HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618 |
| 文件頁數(shù)： | 1/42頁 |
| 文件大?。?/td> | 292K |
| 代理商： | ADC1215S080HN |
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1. General description
The ADC1215S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1215S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode
because of a separate digital output supply.
The ADC1215S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1215S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications because of the integrated input buffer. The input buffer
ensures that the input impedance remains constant and low and the performance
consistent over a wide frequency range.
2. Features and benefits
SNR, 70 dBFS / SFDR, 86 dBc
Sample rate up to 125 Msps
ADC1215S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 2 — 13 January 2011
Product data sheet
Input bandwidth, 600 MHz
Power dissipation, 635 mW at 80 Msps,
including analog input buffer
SPI
Duty cycle stabilizer
12-bit pipelined ADC core
Clock input divided by 2 for less jitter
contribution
Integrated input buffer
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
CMOS or LVDS DDR digital outputs
Pin compatible with the ADC1415S
series, the ADC1015S series and the
ADC1115S125
Fast OuT-of-Range (OTR) detection
Offset binary, two’s complement, gray
code
Power-down and Sleep modes
HVQFN40 package
相關PDF資料 |
PDF描述 |
|---|---|
| ADC1215S105HN | Single 12-bit ADC 105 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| ADC1215S125HN | Single 12-bit ADC 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| ADC1415S065F1 | |
| ADC1415S065HN | Single 14-bit ADC 65 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| ADC1415S065HN | Single 14-bit ADC 65 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1215S080HN/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs |
| ADC1215S080HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 80MSPS IN BUF CMOS/LVDS DDR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1215S080HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk |
| ADC1215S080HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Tape and Reel |
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