參數(shù)資料
型號(hào): ADC12191
廠商: National Semiconductor Corporation
英文描述: 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold(12位10 MHz可自行校對(duì)的管線式帶內(nèi)部采樣和保持功能A/D轉(zhuǎn)換器)
中文描述: 12位,10 MHz的自校準(zhǔn),流水線A / D轉(zhuǎn)換器,內(nèi)置采樣
文件頁(yè)數(shù): 13/16頁(yè)
文件大小: 278K
代理商: ADC12191
Applications Information
(Continued)
5.0 Layout and Grounding
Proper grounding and routing of all signals is essential to
ensure accurate conversion. Separate analog and digital
ground planes that are connected beneath the ADC12191
are required to achieve specified performance. The analog
and digital grounds may be in the same layer, but should be
separated from each other and should never overlap each
other. Separation should be at least 1/8 inch, where
possible.
The ground return for the digital output buffer supply (DGND
I/O) carries the ground current for the output drivers. This pin
should be connected to the system digital ground. The
current on this pin can exhibit high transients that could add
noise to the conversion process. To prevent this from
happening, the DGND I/O pin should NOT be connected in
close proximity to any of the ADC12191’s other ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry
separated from the digital circuitry and from the digital
ground plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have
significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and 74
AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients
during clock or signal edges, like the 74F and the 74AC(T)
families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
rest of the ground plane. This narrowing beneath the
converter provides a fairly high impedance to the high
frequency components of the digital switching currents,
directing them away from the analog pins. The relatively
lower frequency analog ground currents do not create a
significant voltage drop across the impedance of this narrow
ground connection.
To maximize accuracy in high speed, high resolution
systems, avoid crossing analog and digital signal traces. It is
important to keep any clock lines isolated from ALL other
lines. Even the generally accepted 90 degree crossing
should be avoided as even a little coupling can cause
problems at high frequencies. This is because other lines
can introduce phase noise (jitter) into the clock line, which
can lead to degradation of SNR.
DS101040-23
FIGURE 5. Basic Connections Diagram
A
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