- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378284 > ADC121S625EVAL (National Semiconductor Corporation) 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter PDF資料下載
參數(shù)資料
| 型號： | ADC121S625EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter |
| 中文描述： | 12位，50 kSPS的200 ksps的，差動輸入，微功耗采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | ADC121S625EVAL |
Functional Description
(Continued)
TABLE 1. Allowable V
CM
Range
Input Signal
Minimum V
CM
Maximum V
CM
V
A
+ 0.3V
( V
REF
/ 2 )
V
A
+ 0.3V
V
REF
Differential
V
REF
/ 2 0.3V
Single-Ended
V
REF
0.3V
3.0 SERIAL DIGITAL INTERFACE
The ADC121S625 communicates via a synchronous 3-wire
serial interface as shown in the timing diagram. Each output
bit is sent on the falling edge of SCLK. While most receiving
systems will capture the digital output bits on the rising edge
of SCLK, the falling edge of SCLK may be used to capture
each bit if the minimum hold time for D
OUT
is acceptable.
3.1 Digital Inputs
The Digital inputs consist of the SCLK and CS. A falling CS
initiates the conversion and data transfer. The time between
the fall of CS and the second falling edge of SCLK is used to
sample the input signal. The data output is enabled at the
second falling edge of SCLK that follows the fall of CS. Since
the first bit clocked out is a null bit, the MSB is clocked out on
the third falling edge of SCLK after the fall of CS. For the
next 12 SCLK periods D
OUT
will output the conversion result,
most significant bit first.After the least significant bit (B0) has
been output, the output data is repeated if CS remains low
after the LSB is output, but in a least significant bit first
format, with the LSB being output only once, as indicated in
the Double Cycle Timing Diagram. D
OUT
will go into its high
impedance state after the B9 - B10 - B11 sequence. If CS is
raised between prior to or at the 15th clock fall, D
will go
into its high impedance state after the LSB (B0) is output and
the data is not repeated. Additional clock cycles will not
effect the converter. A new conversion is initiated only when
CS has been taken HIGH and returned LOW.
3.1 SCLK Input
The SCLK (serial clock) is used to time the conversion
process and to clock out the conversion results. This input is
TTL/CMOS compatible. Internal settling time limits the maxi-
mum clock frequency and internal capacitor leakage, or
droop,
limits
the
minimum
ADC121S625 offers guaranteed performance with clock
rates in the range indicated in the electrical table.
clock
frequency.
The
3.2 Data Output
The output data format of the ADC121S625 is Two’s
Complement, as shown in
Table 2
. This table indicates the
ideal output code for the given input voltage and does not
include the effects of offset, gain error, linearity errors, or
noise.
TABLE 2. Ideal Output Code vs. Input Voltage
Description
Analog Input
(+IN) (IN)
2’s
Complement
Binary Output
2’s
Comp.
Hex
Code
+ Full Scale
V
REF
1 LSB
0V
0111 1111 1111
7FF
Midscale
Midscale
1 LSB
Full Scale
0000 0000 0000
000
0V 1 LSB
1111 1111 1111
FFF
V
REF
1000 0000 0000
800
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC121S625:
40C
≤
T
A
≤
+85C
+4.5V V
A
≤
+5.5V
0.1V
≤
V
REF
≤
2.5V
0.8 MHz
≤
f
CLK
≤
4.8 MHz
V
CM
: See Section 2.3
20132761
FIGURE 1. V
CM
range for Differential Input operation
20132762
FIGURE 2. V
CM
range for single-ended operation
A
www.national.com
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC121S101EVAL | 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 |
| ADC12281CIVT | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
| ADC12281 | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線式A/D轉(zhuǎn)換器) |
| ADC1241BIJ | Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold |
| ADC1241 | Self-Calibrating 12-Bit Plus Sign μP-Compatible A/D Converter with Sample-and-Hold(可自行校對的12位μP兼容帶采樣和保持功能的A/D轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC121S625EVAL/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ADC121S625 EVAL BOARD RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC121S655 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro Power A/D Converter |
| ADC121S655CIMM | 制造商:Texas Instruments 功能描述:A/D CONVERTER DIFF INPUT MSOP8 |
| ADC121S655CIMM/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC121S655CIMMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro Power A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。