參數(shù)資料
型號(hào)： ADC1225
廠商： National Semiconductor Corporation
元件分類： 串行ADC
英文描述： 12-Bit Plus Sign mP Compatible A/D Converters
中文描述： 12位帶符號(hào)手機(jī)兼容的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 327K
代理商： ADC1225
Electrical Characteristics
(Continued)
The following specifications apply for DV
CC
e
AV
CC
e
5V, V
REF
e
5V, f
CLK
e
1.0 MHz, V
b
e b
5V for bipolar input range, or
V
b
e
GND for unipolar input range unless otherwise specified. Bipolar input range is defined as
b
5.05V
s
V
IN(
a
)
s
5.05V;
b
5.05V
s
V
IN(
b
)
s
5.05V and
l
V
IN(
a
)
b
V
IN(
b
)
l
s
5.05V. Unipolar input range is defined as
b
0.05V
s
V
IN(
a
)
s
5.05V;
b
0.05V
s
V
IN(
b
)
s
5.05V and
l
V
IN(
a
)
b
V
IN(
b
)
l
s
5.05V.
Boldface limits apply from T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C (Notes 3, 4, 5, 6, 7).
Parameter
Conditions
ADC1205CCJ, ADC1225CCD
ADC1205CCJ-1, ADC1225CCD-1
Units
Limit
Typ
Tested
Limit
(Note 9) (Note 10)
Design
Limit
Typ
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
(Note 8)
(Note 8)
DIGITAL AND DC CHARACTERISTICS
(Continued)
V
OUT(1)
, Logical ‘‘1’’ Output
Voltage (Min)
V
CC
e
4.75V
I
OUT
eb
360
m
A
I
OUT
eb
10
m
A
2.4
4.5
2.4
4.5
2.4
4.5
V
V
V
OUT(0)
, Logical ‘‘0’’ Output
Voltage (Max)
V
CC
e
4.75V
I
OUT
e
1.6 mA
0.4
0.4
0.4
V
I
OUT
, TRI-STATE Output Leakage V
OUT
e
0V
Current (Max)
b
0.01
0.01
b
3
3
b
0.01
0.01
b
0.3
0.3
b
3
3
m
A
m
A
V
OUT
e
5V
I
SOURCE
, Output Source Current
(Min)
V
OUT
e
0V
b
12
b
6.0
b
12
b
7.0
b
6.0
mA
I
SINK
, Output Sink Current (Min)
V
OUT
e
5V
16
8.0
16
9.0
8.0
mA
DI
CC
, DV
CC
Supply Current (Max) f
CLK
e
1 MHz, CS
e
1
1
3
1
2.5
3
mA
AI
CC
, AV
CC
Supply Current (Max) f
CLK
e
1 MHz, CS
e
1
I
b
, V
b
Supply Current (Max)
1
3
1
2.5
3
mA
f
CLK
e
1 MHz, CS
e
1
10
100
10
100
100
m
A
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
5.0V, t
r
e
t
f
e
20 ns and T
A
e
25
§
C unless otherwise specified.
Typ
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Limit
Units
Parameter
Conditions
(Note 8)
f
CLK
, Clock Frequency
MIN
MAX
1.0
1.0
0.3
1.5
MHz
MHz
Clock Duty Cycle
MIN
MAX
40
60
%
%
T
C
, Conversion Time
MIN
MAX
MIN
MAX
108
109
108
109
1/f
CLK
1/f
CLK
m
s
m
s
f
CLK
e
1.0 MHz
f
CLK
e
1.0 MHz
t
W(WR)L
, WR Pulse Width
t
ACC
, Access Time (Delay from
Falling Edge of RD to
Output Data Valid) (Max)
MAX
220
350
ns
C
L
e
100 pF
210
340
ns
t
1H
, t
0H
, TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State) (Max)
R
L
e
2k, C
L
e
100 pF
170
290
ns
t
PD(READYOUT)
, RD or WR to
READYOUT Delay (Max)
250
400
ns
t
PD(INT),
RD or WR to Reset of INT
(Max)
250
400
ns
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2:
All voltages are measured with respect to ground, unless otherwise specified.
Note 3:
A parasitic zener diode exists internally from AV
CC
and DV
CC
to ground. This parasitic zener has a typical breakdown voltage of 7 V
DC
.
4
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