參數(shù)資料
型號(hào)： ADC12662CIVF
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold
中文描述： 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44
封裝： PLASTIC, QFP-44
文件頁(yè)數(shù)： 17/23頁(yè)
文件大?。?/td> 495K
代理商： ADC12662CIVF
Applications Information
(Continued)
Since the current flowing through the SENSE lines is essen-
tially zero, there is negligible voltage drop across R
and the
1 k
resistor, so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bottom)
of the ladder. The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps’s non-inverting input, plus or minus
its input offset voltage. For this reason op amps with low
V
, such as the LM627 or LM607, should be used for this
application. When used in this configuration, the ADC12662
has less than 2 LSBs of offset and 1.5 LSB of gain error
without any user adjustments.
The 0.1 μF and 10 μF capacitors on the force inputs provide
high frequency decoupling of the reference ladder. The 500
force resistors isolate the op amps from this large capacitive
load. The 0.01 μF/1 k
network provides zero phase shift at
high frequencies to ensure stability. Note that the op amp
supplies in this example must be
±
10V to
±
15V to meet the
input/output voltage range requirements of the LM627 and
supply the sub-zero voltage to the V
pin. The
V
output should be bypassed to analog ground with a
0.1 μF ceramic capacitor.
The reference inputs are fully differential and define the zero
to full-scale range of the input signal. They can be configured
to span up to 5V (V
= 0V, V
= 5V), or they can be
connected to different voltages (within the 0V to 5V limits)
when other input spans are required. The ADC12662 is
tested at V
= 0V, V
= 4.096V. Re-
ducing the reference voltage span to less than 4V increases
the sensitivity (reduces the LSB size) of the converter; how-
ever noise performance degrades when lower reference
voltages are used. A plot of dynamic performance vs refer-
ence voltage is given in the Typical Performance Character-
istics section.
If the converter will be used in an application where DC
accuracy is secondary to dynamic performance, then a sim-
pler reference circuit may suffice. The circuit shown in Figure
11 will introduce several LSBs of offset and gain error, but
INL, DNL, and all dynamic specifications will be unaffected.
All bypass capacitors should be located as close to the
ADC12662 as possible to minimize noise on the reference
ladder. The V
REF/16
output should be bypassed to analog
ground with a 0.1 μF ceramic capacitor.
The LM4040 shunt voltage reference is available with a
4.096V output voltage. With initial accuracies as low as
±
0.1%, it makes an excellent reference for the ADC12662.
01187622
FIGURE 10. Reference Ladder Force and Sense Inputs
A
www.national.com
17
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