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參數(shù)資料
| 型號： | ADC12L034 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold(可自行校對3.3V12位串行輸入/輸出帶MUX，采樣/保持功能A/D轉(zhuǎn)換器) |
| 中文描述： | 3.3自校準(zhǔn)12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持（可自行校對3.3V12位串行輸入/輸出帶復(fù)用，采樣/保持功能的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 29/36頁 |
| 文件大小： | 819K |
| 代理商： | ADC12L034 |
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Application Hints
(Continued)
3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the V
REF+
and
V
REF
defines the analog input span (the difference between
the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources driving V
REF+
or V
REF
must have
very low output impedance and noise.
The ADC12L030/2/4/8 can be used in either ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC’s reference voltage. When this voltage is the sys-
tem power supply, the V
REF+
pin is connected to V
A+
and
V
REF
is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together.
This maintains the same output code for given input condi-
tions. For absolute accuracy, where the analog input voltage
varies between very specific voltage limits, a time and tem-
perature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage’s magni-
tude will require an initial adjustment to null reference volt-
age induced full-scale errors.
Below are recommended references along with some key
specifications.
Output
Voltage
Tolerance
±
0.5%
±
0.1%
Temperature
Coefficient
(max)
±
100ppm/C
±
100ppm/C
Part Number
LM4041CIM3-Adj
LM4040AIM3-2.5
The reference voltage inputs are not fully differential. The
ADC12L030/2/4/8 will not generate correct conversions or
comparisons if V
REF+
is taken below V
REF
. Correct conver-
sions result when V
REF+
and V
REF
differ by 1V and remain,
at all times, between ground and V
A+
. The V
REF
common
mode range, (V
REF+
+ V
REF
)/2, is restricted to (0.1 x V
A+
) to
(0.6 x V
A+
). Therefore, with V
A+
= 3.3V the center of the
reference ladder should not go below 0.33V or above 1.98V.
Figure 15 is a graphic representation of the voltage restric-
tions on V
REF+
and V
REF
.
DS011830-50
FIGURE 14. Fully Differential Biasing
DS011830-43
FIGURE 15. V
REF
Operating Range
A
www.national.com
29
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