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參數(shù)資料
| 型號： | ADC12L038 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold(可自行校對3.3V12位串行輸入/輸出帶MUX，采樣/保持功能A/D轉(zhuǎn)換器) |
| 中文描述： | 3.3自校準(zhǔn)12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持（可自行校對3.3V12位串行輸入/輸出帶復(fù)用，采樣/保持功能的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 819K |
| 代理商： | ADC12L038 |
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AC Electrical Characteristics
(Continued)
The following specifications apply for V
+
= V
+ = V
+ = +3.3 V
, V
+ = +2.500 V
, V
REF
= 0 V
DC
, 12-bit + sign conver-
sion mode, t
r
= t
f
= 3 ns, f
CK
= f
SK
= 5 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
≤
25
, fully-differential input
with fixed 1.250V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for
T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
t
SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge
Access Time Delay from
CS Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
Delay from SCLK Falling
Edge to CS Falling Edge
Delay from CS Rising Edge to
DO TRI-STATE
DI Hold Time from Serial Data
Clock Rising Edge
DI Set-Up Time from Serial Data
Clock Rising Edge
DO Hold Time from Serial Data
Clock Falling Edge
Delay from Serial Data Clock
Falling Edge to DO Data Valid
DO Rise Time, TRI-STATE to High
DO Rise Time, Low to High
DO Fall Time, TRI-STATE to Low
DO Fall Time, High to Low
Delay from CS Falling Edge
to DOR Falling Edge
Delay from Serial Data Clock Falling
Edge to DOR Rising Edge
Capacitance of Logic Inputs
Capacitance of Logic Outputs
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<
GND or V
>
V
+ or V
+), the current at that pin should be limited to 20 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
θ
and the ambient temperature, T
. The maximum
allowable power dissipation at any temperature is P
D
= (T
max T
)/
θ
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
J
max = 150C. The typical thermal resistance (
θ
JA
) of these parts when board mounted follow:
500
700
μs (max)
t
ACC
25
60
ns (max)
t
SET-UP
50
ns (min)
t
DELAY
0
5
ns (min)
t
1H
, t
0H
R
L
= 3k, C
L
= 100 pF
70
100
ns (max)
t
HDI
5
15
ns (min)
t
SDI
5
10
ns (min)
t
HDO
R
L
= 3k, C
L
= 100 pF
35
65
5
90
ns (max)
ns (min)
ns (max)
t
DDO
50
t
RDO
R
L
= 3k, C
L
= 100 pF
10
10
15
15
50
40
40
40
40
80
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
t
FDO
R
L
= 3k, C
L
= 100 pF
t
CD
t
SD
45
80
ns (max)
C
IN
C
OUT
10
20
pF
pF
A
www.national.com
9
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