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參數(shù)資料
| 型號： | ADC1390X |
| 英文描述： | ADC1390X 8BIT 125MSPS ADC|Data Sheet |
| 中文描述： | ADC1390X 8位125MSPS模數(shù)轉換器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 566K |
| 代理商： | ADC1390X |
SEC ASIC
adc1336x
8BIT 500KSPS ADC
ANALOG
FUNCTIONAL
DESCRIPTION
The XP1 is the system main clock. If 25MHz clock is applied, 8bit 500KSPS outputs are produced. In case
of 10MHz clock, 8bit 250KSPS outputs are made.
1. XP1
This pin is used for keeping standby without A/D conversion operation. For A/D operation, its state must be
changed from '1' to '0' after at least one XP1 period. In the timing chart, 3.5-XP1 period is drawn and this
state transition can occur even at rising or falling edges. If not needed, it can be tied to GND.
2. STBY
This is a A/D conversion enable signal. It is for one XP1 period at falling edge. 37-XP1 periods are
delayed until the next ADEN for an 8bit.
3. ADEN
Digital output pins.
4. DO[7:0]
Data read signal. If DGET is applied during A/D conversion, selected AIN pin information is produced(refer
to TIMING CHART). It is to check if the right analog input is selected. After A/D operation, the state of
the test pin, FLAG, changes to '1', and A/D converted data are produced by applying DGET signal.
5. DGET
Analog Input
6. AIN
Test pin. Its state goes LOW during A/D conversion, and goes HIGH after the A/D conversion. If STBY
signal is applied even at A/D conversion mode, its state goes HIGH immediately.
7. FLAG
6/11
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