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參數(shù)資料
| 型號： | ADC14061CCVT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Self-Calibrating 14-Bit, 2.5 MSPS, 390 mW A/D Converter |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 471K |
| 代理商： | ADC14061CCVT |
AC Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
+
= V
= V
= +5.0V, V
I/O = 3.0V or 5.0V,
PD = +5V, V
+
= +2.0V, V
REF IN
= AGND, f
CLK
= 2.5 MHz, RS = 25
, C
L
= 50 pF/pin. After Auto-Cal
@
Temperature.
Boldface limits apply for T
A
J
= T
MIN
to T
MAX
:
all other limits T
A
= T
J
= 25C(Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
t
OD
Falling Edge of CLK to Data
Valid
Falling edge of CLK to falling
edge of EOC
Falling edge of CLOCK to Data
Valid
Aperture Delay
RD low to data valid on D00
-D13
RD high to D00 -D13 in
TRI-STATE
Calibration Time
50
ns
t
EOCL
1/(4f
CLK
)
90
130
38
95
ns(min)
ns(max)
ns(min)
ns(max)
ns
t
DATA_VALID
1/(8f
CLK
)
t
AD
9
t
ON
23
33
ns(max)
t
OFF
25
33
ns(max)
t
CAL
110
ms
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND = AGND = DGND I/O = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supplies (that is, V
<
AGND or V
>
V
or V
), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4:
The absolute maximum junction temperature (T
max) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (
θ
), and the ambient temperature (T
), and can be calculated using the formula P
MAX = (T
max - T
)/
θ
. In the 52-pin
TQFP,
θ
is 70C/W, so P
MAX = 1,785 mW at 25C and 1,142 mW at the maximum operating ambient temperature of 70C. Note that the power dissipation of this
device under normal operation will typically be about 410 mW (390 mW quiescent power + 20 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC14061 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5k
resistor. Machine model is 220 pF discharged through ZERO
.
Note 6:
See AN450,
″
Surface Mounting Methods and Their Effect on Product Reliability
″
, or the section entitled
″
Surface Mount
″
found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7:
The inputs are protected as shown below. Input voltage magnitudes up to 5V above V
A
or to 5V below GND will not damage this device, provided current
is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above V
A
or below GND by more than 100 mV. As an example, if V
A
is 4.75
V
DC
, the full-cale input voltage must be
≤
4.85V
DC
to ensure accurate conversions
Note 8:
To guarantee accuracy, it is required that V
A
and V
D
be connected together and to the same power supply with separate bypass capacitors at each V
+
pin.
Note 9:
With the test condition for V
REF
= (V
REF
+ V
REF
) given as +2.0V, the 14-bit LSB is 122 μV.
Note 10:
Typical figures are at T
A
= T
J
= 25C, and represent most likely parametric norms.
Note 11:
Tested limits are guaranteed to Nationsl’s AOQL (Average Outgoing Quality Level).
Note 12:
Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13:
Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 14:
Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), the
LM4041CIZ-ADJ (TO-92 package), or the LM4041CIM-ADJ (SO-8 package) bandgap voltage reference is recommended for this application.
DS100103-11
ESD Protection Scheme for Digital Input pins
DS100103-12
ESD Protection Scheme for Analog Input and Digital
Output pins
A
www.national.com
8
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