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參數(shù)資料
| 型號： | ADC5020-M4S |
| 元件分類： | ADC |
| 英文描述： | Analog to Digital Converter |
| 中文描述： | 模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 107K |
| 代理商： | ADC5020-M4S |
Notes:
1. Unless otherwise noted, all specifications apply at 25°C.
Supplies are ±15V and ±5V. Full scale range is ±5V.
2. Reference input is optional. If it is not used, Ref In must be
jumpered to Ref Out.
3. Signal-to-Noise Ratio represents the ratio of the RMS
value of the signal to the total RMS noise below the
Nyquist rate. The total RMS noise is computed by: (1)
summing the noise power in all frequency bins not corre-
lated with the test signal; (2) estimating the total noise
power contained in all harmonic frequency bins; and (3)
computing the RMS noise from the sum of (1) and (2).
4 Peak Distortion represents the ratio of the highest spurious
frequency component below the Nyquist rate to the signal.
Note that in computing Peak Distortion the estimated noise
allocated to the harmonic frequency bins in computing
SNR is first removed. See Note 3.
5. Total Harmonic Distortion represents the ratio of the RMS
sum of all harmonics up to the 100th harmonic to the RMS
value of the signal. Note that in computing Total Harmonic
Distortion the estimated noise allocated to the harmonic fre-
quency bins in computing SNR is first removed. See Note 3.
6 Analysis bandwidth is DC to 20 kHz with 3.5V RMS input
signal.
7. ADC5030 tested and guaranteed with Analogic’s
SHA2410 Sample-and-Hold.
8. Measured with 10V p-p at 25 kHz.
9. Refer to “Output Coding and Trim Procedure” for field ad-
justable gain and offset procedures.
10.With use of internal reference only.
11.Includes noise from S/H and A/D converter.
12.See Ordering Guide.
13.For 0 to 10V range (ADC5020/ADC5030-1) Min. supplies
are ±14.55V.
14.Analogic highly recommends the use of linear power sup-
plies with its high performance, high resolution A/D convert-
ers. However, if system requirements provide only a +5V
supply and limited space, the use of the Analogic SP7008
DC-to-DC converter will provide a low noise solution which
will not degrade the ADC5020/ADC5030 performance.
Specifications subject to change without notice.
ADC5020/ADC5030 SPECIFICATIONS
Output Coding and Trim Procedure
Figure 2 shows the output coding of the ADC5020/
ADC5030 A/D converter. The symbol * in Figure 2 indi-
cates a bit that is undergoing a 0/1 or 1/0 code transi-
tion at the indicated analog input voltage.
To trim the offset of the ADC5020/ADC5030, apply
19 μV to the analog input. Adjust the offset trim poten-
tiometer such that the digital output corresponds to the
truth table of Figure 2.
To trim the gain of the ADC5020/ADC5030, apply
+4.999981V for the bipolar option or +9.999943V for
the unipolar option. Adjust the gain trim potentiometer
such that the digital output corresponds to the truth
table of Figure 2.
In addition to the internal offset and gain potentiome-
ters, provisions have been made to dynamically null
out DC errors by use of external potentiometers or
DACs. The ratio of A/D converter DC shift to the exter-
nal control voltage is 500 μV/V. A 10V swing from a
DAC on Pin 12 produces a 5 mV offset shift, a 10V
swing on Pin 32 produces a 5 mV gain shift.
Timing Considerations
The timing diagram in Figure 3 shows the timing char-
acteristics of the ADC5020/ADC5030 A/D converter.
Upon a low-to-high transition of the Trigger Input, the
end of conversion (EOC) line also switches high. The
EOC line in turn switches the internal sample-and-hold
amplifier to Hold mode; the S/H amplifier remains in
Hold mode for the 5 μs duration of the A/D conversion
period. At the end of the 5 μs A/D conversion period,
the EOC line goes low and switches the sample-and-
hold amplifier to Sample mode. At the 144 kHz
throughput rate shown in Figure 3, the sample-and-
hold amplifier then has 1.9 μs to sample (acquire) a
new signal level for the next conversion cycle. The
TTL-level Trigger input should have a minimum pulse
width of 50 ns. Note that the data for a given conver-
sion cycle becomes valid approximately 20 ns before
the respective high-to-low transition of the EOC line.
Truth Table
Digital Outputs
Input Voltage
Comp. Offset Binary
MSB LSB
Straight Offset Binary
MSB LSB
Bipolar
5.000000V
4.999981V
4.999962V
0000000000000000
000000000000000*
0000000000000001
1111111111111111
111111111111111*
1111111111111110
+0.000038V
+0.000019V
0.000000V
0111111111111111
****************
1000000000000000
1000000000000000
****************
0111111111111111
–4.999924V
–4.999943V
–4.999962V
1111111111111110
111111111111111*
1111111111111111
0000000000000001
000000000000000*
0000000000000000
Unipolar
9.999962V
9.999943V
9.999924V
0000000000000000
000000000000000*
0000000000000001
1111111111111111
111111111111111*
1111111111111110
+5.000000V
+4.999981V
+4.999962V
0111111111111111
****************
1000000000000000
1000000000000000
****************
0111111111111111
+0.000038V
+0.000019V
+0.000000V
1111111111111110
111111111111111*
1111111111111111
0000000000000001
000000000000000*
0000000000000000
Figure 2. Output Coding for the
ADC5020/ADC5030.
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| ADC5030-M1C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
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| ADC5030-M4C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
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