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參數(shù)資料
| 型號(hào)： | ADC574AJH |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:53; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:18-53 RoHS Compliant: No |
| 中文描述： | 微處理器兼容模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大小： | 103K |
| 代理商： | ADC574AJH |
9
ADC574A
desired. When 12/8 is high, all 12 output lines (DB0–DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the A
O
state is ignored.
When 12/8 is low, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A
O
during the read cycle. Connection
of the ADC574A to an 8-bit bus for transfer of left-justified
data is illustrated in Figure 8. The A
O
input is usually driven
by the least significant bit of the address bus, allowing
storage of the output data word in two consecutive memory
locations.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and A
O
. See Figure 7 and Table V for timing relation-
ships and specifications.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTL-
and CMOS-compatible and may be actively driven if
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
C
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
A
O
to CE setup
A
valid during CE high
Conversion time, 12-bit cycle
8-bit cycle
60
30
20
20
0
20
200
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
50
50
50
50
50
0
50
15
10
20
20
13
25
17
Read Mode
t
DD
t
HD
t
HL
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
t
HS
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
A
O
to CE setup
CS valid after CE low
R/C high after CE low
A
valid after CE low
STS delay after data valid
75
35
100
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
150
50
0
50
0
0
50
300
25
400
1000
NOTE: Specifications are at +25
°
C and measured at 50% level of transitions.
TABLE V. Timing Specifications.
FIGURE 7. Read Cycle Timing.
FIGURE 6. Conversion Cycle Timing.
CE
t
HEC
t
SSC
t
SRC
t
HSC
t
HRC
t
HAC
t
SAC
t
DSC
t
C
High Impedance
CS
R/C
STS
DB11–
DB0
A
O
CE
t
SSR
t
SRR
t
HRR
t
HS
t
HD
High-Z
CS
R/C
STS
DB11–
DB0
t
HSR
A
O
t
HAR
t
SAR
Data Valid
t
HL
t
DD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC574AJP | JT 53C 53#20 SKT PLUG |
| ADC574AKP | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC574A | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC574ASH | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC574ATH | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC574AJN | 制造商:BURR-BROWN 功能描述: 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:Part Number Only |
| ADC574AJP | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC574AK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| ADC574AKD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| ADC574AKH | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
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