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參數資料
| 型號： | ADC674AKH |
| 英文描述： | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 微處理器兼容模擬到數字轉換器 |
| 文件頁數： | 6/6頁 |
| 文件大?。?/td> | 56K |
| 代理商： | ADC674AKH |
6
ADC674A
NOTE: Specifications are at + 25
°
C and measured at 50% level of transitions.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
t
C
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High
R/C to CE Setup
R/C Low During CE High
A
O
To CE Setup
A
O
Valid During CE high
Conversion Time, 12 Bit Cycle
60
30
20
20
0
20
200
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
50
50
50
50
50
0
50
9
6
20
12
8
15
10
8 Bit Cycle
Read Mode
t
DD
t
HD
t
HL
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
t
HS
Access Time From CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
R/C to CE Setup
A
O
to CE Setup
CS Valid After CE Low
R/C high After CE Low
A
O
Valid
After CE Low
STS delay After Data Valid
75
35
100
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
150
50
0
50
25
0
0
50
300
100
600
TABLE IV. Timing Specifications
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if A
O
changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of A
O
, possibly resulting
in an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and A
O
. See Figure 4 and Table IV for timing relation-
ships and specifications.
FIGURE 4. Read Cycle Timing.
CE
t
SSR
CS
A
O
Data Valid
DB11-DB0
High-Z
STATUS
R/C
t
SRR
t
SAR
t
DD
t
HS
t
HL
t
HD
t
HAR
t
HRR
t
HSR
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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相關代理商/技術參數 |
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| ADC674AKP | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC674AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| ADC674AS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| ADC674AS/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| ADC674ASH | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
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