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參數(shù)資料
| 型號(hào)： | ADC700AH |
| 英文描述： | 16-Bit Resolution With Microprocessor Interface A/D CONVERTER |
| 中文描述： | 16位分辨率，微處理器接口的A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | ADC700AH |
11
ADC700
FIGURE 10. Serial Data Output Providing Convenient
Isolation.
Isolation Barrier
V
DD
V
DD
Serial
Data
Strobe
Reset
Serial
Data
ADC700
FIGURE 11. Continuous Conversion Circuit Connection.
ADC700
WR
CS
Status
To Interrupt
PIN DESIGNATION
DEFINITION
FUNCTION
CS (Pin 9)
WR (Pin 7)
RD (Pin 8)
HBEN (Pin 10)
Chip Select
Write (Convert)
Read
High Byte Enable
“1” = Low Byte
“0” = High Byte
Reset
Must be Low to either initiate a conversion or read output data.
Conversion begins after the High-to-Low transition.
Turns ON the three-state output drivers upon being asserted low.
Selects the MSB or the LSB for readout. Data Ready is cleared when HBEN is Low and RD is asserted.
Reset (Pin 6)
Resets internal logic. Must be asserted after power-up or a power interruption clears Status and Data
Ready to Low.
Sets the output code to Binary Twos Complement (BTC) when Low. Output code is Bipolar Offset Binary
(BOB) when High.
BTCEN (Pin 23)
BTC Enable
TABLE III. Control Line Functions.
TABLE IV. Control Input Truth Table.
CONTROL LINE
RESET
WR
RD
HBEN
CS
OPERATION
0
1
1
1
1
1
1
X
X
0
1
1
0
0
X
X
X
0
0
0
0
X
X
X
0
1
0
1
X
1
0
0
0
0
0
Reset converter logic. Status and Data Ready set Low.
No operation.
Initiate conversion.
Places High Byte on output port. Clears Data Ready flag.
Placed Low Byte on output port. Does not clear Data Ready flag.
Initiates conversion and places High Byte or output port. Clears Data Ready.
Initiates conversion and places Low Byte on output port. Does not clear Data Ready flag.
NOTE: If a conversion command is asserted while a conversion is in progress, the command is ignored. If the conversion command remains asserted when a
conversion is finished, a new conversion will begin.
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